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    Method for receiving optical orthogonal frequency-division multiplexing signal and receiver thereof
    1.
    发明授权
    Method for receiving optical orthogonal frequency-division multiplexing signal and receiver thereof 有权
    用于接收光正交频分复用信号的方法及其接收机

    公开(公告)号：US08107817B2

    公开(公告)日：2012-01-31

    申请号：US12464608

    申请日：2009-05-12

    申请人： Yu-Min Lin ,  Dar-Zu Hsu ,  Hung-Lin Chen

    发明人： Yu-Min Lin ,  Dar-Zu Hsu ,  Hung-Lin Chen

    IPC分类号： H04J14/02

    CPC分类号： H04L27/2662 ,  H04L27/2672 ,  H04L27/2675 ,  H04L27/2697

    摘要： A method for receiving an optical orthogonal frequency-division multiplexing (OFDM) signal and a receiver thereof are applicable to an optical OFDM system. The receiving method includes the following steps. An optical signal is converted into a digital signal. A symbol boundary of the digital signal is estimated. A guard interval of the digital signal is removed according to the symbol boundary, so as to generate an electrical signal. The electrical signal is converted into a plurality of frequency domain sub-carriers in a fast Fourier transform (FFT) manner. A timing offset is estimated with pilot carriers and frequency domain sub-carriers corresponding to the same symbol period. The estimated symbol boundary is compensated with the timing offset. Each frequency domain sub-carrier includes a plurality of pilot carrier signals. Through the receiving method, the timing offset arisen from chromatic dispersion of an optical fiber is effectively estimated and adopted for compensation.

    摘要翻译： 用于接收光正交频分复用（OFDM）信号的方法及其接收机可应用于光OFDM系统。 接收方法包括以下步骤。 光信号被转换为数字信号。 估计数字信号的符号边界。 根据符号边界去除数字信号的保护间隔，以产生电信号。 电信号以快速傅立叶变换（FFT）方式转换成多个频域子载波。 使用对应于相同符号周期的导频载波和频域子载波来估计定时偏移。 估计的符号边界用定时偏移补偿。 每个频域子载波包括多个导频载波信号。 通过接收方式，可以有效地估计出采用光纤色散引起的定时偏移补偿。

    FAST FOURIER TRANSFORM PROCESSOR
    2.
    发明申请
    FAST FOURIER TRANSFORM PROCESSOR 审中-公开
    快速傅立叶变换处理器

    公开(公告)号：US20100169402A1

    公开(公告)日：2010-07-01

    申请号：US12400794

    申请日：2009-03-10

    申请人： Hung-Lin Chen ,  Yu-Min Lin ,  Dar-Zu Hsu ,  Yuan Chen ,  Chen-Yi Lee

    发明人： Hung-Lin Chen ,  Yu-Min Lin ,  Dar-Zu Hsu ,  Yuan Chen ,  Chen-Yi Lee

    IPC分类号： G06F17/14

    CPC分类号： G06F17/142

    摘要： An FFT processor is disclosed, which includes a first multi-pipelined MDC unit, a second multi-pipelined MDC unit and a switching network. The first multi-pipelined MDC unit and the second multi-pipelined MDC unit respectively employ a plurality of MDC circuits to change the positions of the delayers thereof in parallel way. By changing the operation time sequence of the signals in the first multi-pipelined MDC unit and the second multi-pipelined MDC unit, the first multi-pipelined MDC unit is able to directly send the operation results to the second multi-pipelined MDC unit through the switching network.

    摘要翻译： 公开了一种FFT处理器，其包括第一多流水线MDC单元，第二多流水线MDC单元和交换网络。 第一多流水线MDC单元和第二多流水线MDC单元分别采用多个MDC电路以并行方式改变其延迟器的位置。 通过改变第一多流水线MDC单元和第二多流水线MDC单元中的信号的操作时间顺序，第一多流水线MDC单元能够直接将操作结果发送到第二多流水线MDC单元 交换网络。

    FABRICATING METHOD OF ACTIVE DEVICE ARRAY SUBSTRATE
    4.
    发明申请
    FABRICATING METHOD OF ACTIVE DEVICE ARRAY SUBSTRATE 审中-公开
    主动装置阵列基板的制作方法

    公开(公告)号：US20120270392A1

    公开(公告)日：2012-10-25

    申请号：US13537054

    申请日：2012-06-29

    申请人： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

    发明人： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

    IPC分类号： H01L21/768

    CPC分类号： C23C14/165 ,  C23C14/3492 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

    摘要： A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

    摘要翻译： 提供了一种有源器件阵列衬底的制造方法。 有源器件阵列衬底具有至少一个图案化导电层。 图案化导电层包括铜层。 铜层的与铜层的法线平行的截面包括层叠在第一梯形上的第一梯形和第二梯形。 第一梯形的底角和第二梯形的底角是锐角，第一梯形的底角与第二梯形的底角之间的差为约5°至约30°。

    Electrode connection structure of speaker unit
    5.
    发明授权
    Electrode connection structure of speaker unit 有权
    扬声器单元的电极连接结构

    公开(公告)号：US08280081B2

    公开(公告)日：2012-10-02

    申请号：US12344270

    申请日：2008-12-25

    申请人： Yu-Min Lin ,  Chang-Ho Liou ,  Yu-Wei Huang ,  Ming-Daw Chen ,  Rong-Shen Lee

    发明人： Yu-Min Lin ,  Chang-Ho Liou ,  Yu-Wei Huang ,  Ming-Daw Chen ,  Rong-Shen Lee

    IPC分类号： H04R25/00

    CPC分类号： H04R1/06

    摘要： An electrode connection structure of a speaker unit is provided. The speaker unit includes at least one electrode layer, which is made of a conductive material, or made of a non-conductive material with a conductive layer formed on a surface thereof. The electrode connection structure includes a conductive electrode and an adhesive material. The conductive electrode is used for providing power supply signals for the speaker unit to generate sounds. The adhesive material adheres the conductive electrode in parallel with a surface of the electrode layer. The adhesive material has adhesive characteristics, so as to electrically connect the conductive electrode and the electrode layer, in which the adhesive material is adhered to a side of the surface of the electrode layer closely adjacent to the conductive electrode with a certain area.

    摘要翻译： 提供扬声器单元的电极连接结构。 扬声器单元包括至少一个电极层，该电极层由导电材料制成，或由其表面上形成有导电层的非导电材料制成。 电极连接结构包括导电电极和粘合材料。 导电电极用于为扬声器单元提供电源信号以产生声音。 粘合剂材料将导电电极与电极层的表面平行地粘合。 粘合剂材料具有粘合特性，以便以一定面积将导电电极和电极层电连接，其中粘合剂材料粘附到与导电电极紧密相邻的电极层的表面的一侧。

    HEATING ASSEMBLY, HEATING DEVICE, AND AUXILIARY COOLING MODULE FOR A BATTERY
    6.
    发明申请
    HEATING ASSEMBLY, HEATING DEVICE, AND AUXILIARY COOLING MODULE FOR A BATTERY 有权
    加热装置，加热装置和电池辅助冷却模块

    公开(公告)号：US20110198335A1

    公开(公告)日：2011-08-18

    申请号：US12725467

    申请日：2010-03-17

    申请人： Yu-Min Lin

    发明人： Yu-Min Lin

    IPC分类号： H05B1/00 ,  F28F7/00

    CPC分类号： H05B3/22 ,  F28D1/0477 ,  F28F1/22 ,  H01M10/613 ,  H01M10/615 ,  H01M10/637 ,  H01M10/647 ,  H01M10/6554 ,  H01M10/6556 ,  H01M10/6567 ,  H01M10/6571 ,  H01M10/658

    摘要： The present invention relates to a heating assembly, a heating device and an auxiliary cooling module for a battery. The heating assembly is connected to a battery and includes a heat-conducting element and a heating element. The heat-conducting element has at least one heat-absorbing portion and at least one heat-conducting portion. The heat-conducting portion is provided to correspond to the battery. The heating element has at least one first heating portion located to correspond to the heat-absorbing portion for heating the heat-absorbing portion. The other side of the heat-conducting element opposite to the battery is provided with a heat-insulating portion. The auxiliary cooling module is further provided with at least one cooling pipe in the heat-conducting element, thereby cooling the battery. With the heating assembly, the heating device, and the auxiliary cooling module of the present invention, the battery can be kept in a normal range of working temperature, so that the efficiency and lifetime of the battery can be increased greatly.

    摘要翻译： 本发明涉及一种用于电池的加热组件，加热装置和辅助冷却模块。 加热组件连接到电池并且包括导热元件和加热元件。 导热元件具有至少一个吸热部分和至少一个导热部分。 导热部设置成对应于电池。 加热元件具有至少一个第一加热部分，其被定位成对应于用于加热吸热部分的吸热部分。 与电池相对的导热元件的另一侧设置有绝热部。 辅助冷却模块还在导热元件中设置有至少一个冷却管，从而冷却电池。 利用本发明的加热组件，加热装置和辅助冷却模块，电池可以保持在正常的工作温度范围内，从而可以大大提高电池的使用寿命。

    BUST-MODE CLOCK AND DATA RECOVERY CIRCUIT USING PHASE SELECTING TECHNOLOGY
    7.
    发明申请
    BUST-MODE CLOCK AND DATA RECOVERY CIRCUIT USING PHASE SELECTING TECHNOLOGY 有权
    使用相位选择技术的BUST模式时钟和数据恢复电路

    公开(公告)号：US20100040182A1

    公开(公告)日：2010-02-18

    申请号：US12266530

    申请日：2008-11-06

    申请人： Ching-Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

    发明人： Ching-Yuan Yang ,  Jung-Mao Lin ,  Yu-Min Lin

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0041 ,  H04L7/0087 ,  H04Q11/0067 ,  H04Q2011/0079

    摘要： A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.

    摘要翻译： 提供了采用相位选择技术的突发模式时钟和数据恢复电路。 在数据恢复电路中，使用锁相环（PLL）电路来提供多个具有时钟相位的固定时钟信号。 过采样相位选择电路耦合到锁相环电路，用于通过使用时钟信号检测接收数据信号的数据沿，并根据数据沿的位置选择要锁定的时钟相位。 延迟锁定回路（DLL）电路耦合到锁相环电路和过采样相位选择电路，并用于将数据信号的数据相位与所选择的时钟信号的时钟相位进行比较，以便延迟 数据信号的数据相位延迟一个延迟时间，直到数据相位被锁定为时钟相位。