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    Method and apparatus for providing cancellation of harmonics signals with modulated signals for multi-channels
    1.
    发明授权
    Method and apparatus for providing cancellation of harmonics signals with modulated signals for multi-channels 有权
    用于提供多通道调制信号的谐波信号消除的方法和装置

    公开(公告)号：US07809094B2

    公开(公告)日：2010-10-05

    申请号：US11872667

    申请日：2007-10-15

    Applicant: Junyi Xu ,  Binfan Liu ,  Vladimir Radionov ,  Weimin Zhang

    Inventor： Junyi Xu ,  Binfan Liu ,  Vladimir Radionov ,  Weimin Zhang

    IPC: H03D1/04

    CPC classification number: H04B1/0475

    Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.

    Abstract translation: 用于消除或衰减谐波噪声而不使输入信号失真的装置和方法。 示例性装置包括使用估计环路来产生人造信号以消除或衰减谐波的影响。 估计环路包括适于通过处理或组合输入信号和人造信号来产生混合信号的混频器。 估计回路包括误差检测器，低通滤波器，参数估计器和数控振荡器。 参数估计器产生与输入谐波支路的相位，频率和幅度相关的信息，并由数控振荡器用于产生人为信号。 如果混合信号包含较低水平的谐波残差，则在输出端产生混合信号来代替输入信号。

    Method and system for multi-program clock recovery and timestamp correction
    2.
    发明申请
    Method and system for multi-program clock recovery and timestamp correction 失效
    多程序时钟恢复和时间戳校正的方法和系统

    公开(公告)号：US20060136768A1

    公开(公告)日：2006-06-22

    申请号：US10996582

    申请日：2004-11-23

    Applicant: Binfan Liu ,  Thomas Ayers ,  Weimin Zhang

    Inventor： Binfan Liu ,  Thomas Ayers ,  Weimin Zhang

    IPC: G06F1/12

    CPC classification number: H04N21/4305 ,  H04N5/4401 ,  H04N21/4307

    Abstract: A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.

    Abstract translation: 解码器包括被配置为接收节目并提取嵌入在节目中的定时信息和时间戳的传输引擎。 加法器被配置为将一组定时偏移量添加到定时信息组，以便从第一时间基准到第二时间基准来调整定时信息。 定时偏移和定时信息的和被称为映射定时信息。 校正引擎被配置为在程序中遇到定时信息时更新定时偏移，并且偏移寄存器被配置为：接收定时偏移，存储定时偏移，并将定时偏移传送给加法器。 加法器还被配置为将时间偏移量添加到时间戳，以便调整从第一时间到第二时间的时间戳的时间基准。 程序是被配置为接收调整的时间戳以解码程序的解码器。

    Multi-stream access scheme for high speed access and recording using a hard disk drive
    3.
    发明申请
    Multi-stream access scheme for high speed access and recording using a hard disk drive 有权
    使用硬盘驱动器进行高速访问和记录的多流访问方案

    公开(公告)号：US20030131191A1

    公开(公告)日：2003-07-10

    申请号：US10305260

    申请日：2002-11-25

    Applicant: BroadLogic Network Technologies, Inc.

    Inventor： Weimin Zhang ,  Tony Francesca

    IPC: G06F012/00

    CPC classification number: G11B20/10 ,  G11B2020/1074

    Abstract: A system for facilitating high-speed access and recording is provided. The system includes a demodulator, an buffer memory and a hard disk. During a write cycle, the demodulator is used to receive one or more content streams. The content streams received by the demodulator are first stored in the buffer memory. When the buffer memory has reached its storage capacity, its contents are then transferred to the hard disk for storage. During a read cycle, contents from the hard disk are read and then stored in the buffer memory. Other components of the system can then access the read-out contents from the buffer memory. The amount of contents retrieved from the hard disk and stored in the buffer memory may be more than what is requested depending on the application requesting the contents. The hard disk further includes different zones. There are two types of zones, namely, high-speed zone and random-access zone. The two different types of zones allow for a number of operating modes, namely, the high-speed mode, the random-access mode and the buffer-cleaning mode. In the high-speed mode, contents from the buffer memory are transferred to the high-speed zone in a continuous manner regardless of the nature or classification of the contents. In the random-access mode, contents from the buffer memory are respectively transferred to the appropriate locations in the random-access zone based on the nature or classification of the contents. In the buffer-cleaning mode, contents stored in the high-speed zone are transferred to appropriate locations in the random-access zone based on the nature or classification of the contents.

    Abstract translation: 提供了一种便于高速访问和记录的系统。 该系统包括解调器，缓冲存储器和硬盘。 在写周期期间，解调器用于接收一个或多个内容流。 由解调器接收的内容流首先存储在缓冲存储器中。 当缓冲存储器达到其存储容量时，其内容将被传送到硬盘进行存储。 在读取周期中，读取硬盘中的内容，然后存储在缓冲存储器中。 然后，系统的其他组件可以从缓冲存储器访问读出的内容。 根据请求内容的应用程序，从硬盘检索并存储在缓冲存储器中的内容量可能大于请求的内容。 硬盘还包括不同的区域。 有两种类型的区域，即高速区和随机接入区。 两种不同类型的区域允许多种操作模式，即高速模式，随机访问模式和缓冲清理模式。 在高速模式中，无论内容的性质或分类如何，来自缓冲存储器的内容都以连续的方式被传送到高速区。 在随机访问模式中，根据内容的性质或分类，将来自缓冲存储器的内容分别传送到随机访问区域中的适当位置。 在缓冲清理模式中，基于内容的性质或分类，将存储在高速区中的内容传送到随机存取区中的适当位置。

    High Throughput Interleaver/De-Interleaver
    5.
    发明申请
    High Throughput Interleaver/De-Interleaver 有权
    高吞吐量交织器/去交织器

    公开(公告)号：US20130212328A1

    公开(公告)日：2013-08-15

    申请号：US13725109

    申请日：2012-12-21

    Applicant: BroadLogic Network Technologies Inc.

    Inventor： Binfan Liu ,  Junyi Xu

    IPC: G11C7/10

    CPC classification number: G11C7/1072 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/2936

    Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

    Abstract translation: 提供了使用外部DDR SDRAM执行高速多通道前向纠错的系统和方法。 根据一个示例性方面，交织器/去交织器对通过隐藏有效和预充电周期而突发定向的DDR SDRAM执行读取和写入访问，以便实现高数据速率操作。 交织器/解交织器将DDR SDRAM中的数据作为读取块和写入块访问。 每个块包括两个数据序列。 每个数据序列还包括要交织/解交织的预定数量的数据字。 当处理前面的数据序列时，会发出一个数据序列的PRECHARGE和ACTIVE命令。 一个读/写数据序列中的数据在DDR SDRAM的同一组内具有相同的行地址。

    Techniques for optimizing use of channel bandwidth in on-demand content delivery systems
    6.
    发明授权
    Techniques for optimizing use of channel bandwidth in on-demand content delivery systems 有权
    在按需内容传送系统中优化信道带宽使用的技术

    公开(公告)号：US07624415B1

    公开(公告)日：2009-11-24

    申请号：US10420547

    申请日：2003-04-17

    Applicant: WeiMin Zhang ,  Jeremy Woodburn

    Inventor： WeiMin Zhang ,  Jeremy Woodburn

    IPC: H04N7/173

    CPC classification number: H04N7/17318 ,  H04N21/26616 ,  H04N21/4331 ,  H04N21/47202

    Abstract: A system for optimizing bandwidth of a video-on-demand system is provided. According to one aspect of the system, upon receiving a request from a first subscriber for a program, the system delivers the program to the first subscriber via a first communication channel. Upon receiving a request from a second subscriber for the same program, the system delivers only a beginning portion of the program to the second subscriber via a second communication channel and at the same time records a remaining portion of the program from the first communication channel. At the appropriate time, the recorded remaining portion of the program are shown to the second subscriber.

    Abstract translation: 提供了一种用于优化视频点播系统的带宽的系统。 根据系统的一个方面，在从第一用户接收到用于节目的请求时，系统经由第一通信信道将节目传送给第一用户。 在从同一程序的第二用户接收到请求时，系统经由第二通信信道仅将节目的开始部分传送给第二用户，同时从第一通信信道记录节目的剩余部分。 在适当的时间，向第二用户显示节目的记录剩余部分。

    Digital two-stage automatic gain control
    7.
    发明授权
    Digital two-stage automatic gain control 失效
    数字两级自动增益控制

    公开(公告)号：US07460623B1

    公开(公告)日：2008-12-02

    申请号：US10360834

    申请日：2003-02-06

    Applicant: Vladimir Radionov ,  Ryan Yu

    Inventor： Vladimir Radionov ,  Ryan Yu

    IPC: H04L27/08

    CPC classification number: H03G3/3089 ,  H03G2201/202 ,  H03G2201/302

    Abstract: A digital automatic gain control circuit is disclosed. The circuit includes a selector, a scaler, a detector, a gain adjustor and a controller. In one exemplary aspect, the selector receives an input signal having two components, namely, the in-phase (I) and quadrature (Q) components, in digital form. The selector then selects a subset of bits from each component based on a control signal provided by the controller. The two subsets are then forwarded to the scaler. The scaler then multiplies the two subsets respectively against a gain value to generate two multiplication results. A portion of each multiplication result is then provided as output by the scaler. The gain value and the subset selection are periodically adjusted in response to the scaler output. The adjustments with respect to the gain value and the subset selection are effectuated collectively by the detector, the gain adjustor and the controller.

    Abstract translation: 公开了一种数字自动增益控制电路。 该电路包括选择器，定标器，检测器，增益调节器和控制器。 在一个示例性方面，选择器以数字形式接收具有两个分量的输入信号，即同相（I）和正交（Q）分量。 然后，选择器基于由控制器提供的控制信号从每个分量中选择一个比特的子集。 然后将两个子集转发到缩放器。 缩放器然后将两个子集分别乘以增益值以生成两个相乘结果。 然后将每个乘法结果的一部分作为缩放器的输出提供。 响应于缩放器输出周期性地调整增益值和子集选择。 相对于增益值和子集选择的调整由检测器，增益调节器和控制器共同实现。

    Method and system for providing a multi-channel interleaver/deinterleaver using SDRAM
    8.
    发明授权
    Method and system for providing a multi-channel interleaver/deinterleaver using SDRAM 有权
    使用SDRAM提供多通道交织器/解交织器的方法和系统

    公开(公告)号：US07051171B1

    公开(公告)日：2006-05-23

    申请号：US10412713

    申请日：2003-04-11

    Applicant: Binfan Liu ,  Zhongqiang Wang ,  Thomas Ayers

    Inventor： Binfan Liu ,  Zhongqiang Wang ,  Thomas Ayers

    IPC: G06F12/00

    CPC classification number: G06F11/1008

    Abstract: A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM.

    Abstract translation: 提供了一种使用外部SDRAM执行高速多通道前向纠错的去交织器。 根据一个示例性方面，解交织器通过隐藏有效和预充电周期对SDRAM进行读取和写入访问，以实现高数据速率操作。 SDRAM的数据总线长度设计为解交织符号大小的两倍，从而允许增加带宽。 解交织器将SDRAM中的数据作为读取块和写入块访问。 每个块包括要交织/去交错的预定数量的数据字。 当前一个块被处理时，发出一个块的ACTIVE命令。 一个读/写块中的数据在SDRAM的同一组内具有相同的行地址。

    Multi-threaded direct memory access engine for broadcast data demultiplex operations
    9.
    发明授权
    Multi-threaded direct memory access engine for broadcast data demultiplex operations 有权
    用于广播数据解复用操作的多线程直接存储器访问引擎

    公开(公告)号：US07000244B1

    公开(公告)日：2006-02-14

    申请号：US09651539

    申请日：2000-08-29

    Applicant: Thomas G. Adams ,  Gene Maine

    Inventor： Thomas G. Adams ,  Gene Maine

    IPC: H04N7/173 ,  G06F3/00 ,  G06F11/00 ,  H04J3/24 ,  H04J3/00

    CPC classification number: H04N21/42692 ,  H04N21/235 ,  H04N21/23614 ,  H04N21/434 ,  H04N21/4348 ,  H04N21/435

    Abstract: A method and system for transferring a transport stream, such as from a satellite receiver to a networked computer system, are provided. The transport stream is parsed to derive multiple elementary streams including associated program identifiers, which are used to determine corresponding transfer locations in a host memory. Direct memory access transfers of the multiple elementary streams are then performed to the corresponding transfer locations in the host memory.

    Abstract translation: 提供了一种用于将诸如从卫星接收机传送到网络计算机系统的传输流的方法和系统。 传输流被解析以导出包括相关联的节目标识符的多个基本流，其用于确定主机存储器中相应的传送位置。 然后，将多个基本流的直接存储器访问传输执行到主机存储器中的相应传送位置。

    Error correction coding across multiple channels in content distribution systems
    10.
    发明申请
    Error correction coding across multiple channels in content distribution systems 有权
    内容分发系统中多个通道的纠错编码

    公开(公告)号：US20030167432A1

    公开(公告)日：2003-09-04

    申请号：US10087202

    申请日：2002-03-01

    Applicant: BroadLogic Network Technologies, Inc.

    Inventor： Wei-Min Zhang ,  Timothy A. Misko

    IPC: H04L001/00 ,  G06F011/00

    CPC classification number: H03M13/29 ,  H03M13/2978 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0076 ,  H04L25/14

    Abstract: Error correction coding across multiple channels is provided in multi-channel transmission systems. Specifically, redundancy is provided by selecting a portion of original data from each of a plurality of original channels, performing at least one encoding operation using the portions of original data to produce at least one portion of redundancy data, including the portion of redundancy data in at least one redundancy channel, and transmitting the redundancy channel along with the original channels. Error correction is achieved by receiving at least one redundancy channel and a plurality of original channels, selecting a portion of redundancy data from the redundancy channel, selecting a portion of original data from each of the original channels, and performing at least one decoding operation using the portion of redundancy data and the portions of original data to correct at least one error in the portions of original data.

    Abstract translation: 在多信道传输系统中提供了跨多个信道的纠错编码。 具体地，通过从多个原始信道中的每一个选择一部分原始数据来提供冗余，使用原始数据的部分执行至少一个编码操作，以产生冗余数据的至少一部分，包括冗余数据的一部分 至少一个冗余信道，并且与原始信道一起发送冗余信道。 通过接收至少一个冗余信道和多个原始信道，从冗余信道中选择冗余数据的一部分，从每个原始信道中选择一部分原始数据，并使用 冗余数据的部分和原始数据的部分以校正原始数据的部分中的至少一个错误。

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