公开(公告)号：US09236479B2

公开(公告)日：2016-01-12

申请号：US14708405

申请日：2015-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/78603

Abstract: One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.

公开(公告)号：US09324631B2

公开(公告)日：2016-04-26

申请号：US13870411

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Axel Walter ,  Matthias Lehr

IPC: H01L23/58 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L23/481 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06133 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.

Abstract translation: 形成在复合半导体器件的金属化系统之上的凸起结构或柱结构可以包括应力缓冲层，其可以有效地分布由于这些部件的热失配而在芯片封装相互作用期间通常发生的所得到的机械应力。 应力缓冲层包括覆盖整个表面的重要部分的铜基缓冲区，其中也可以使用约3-10μm的厚度。 此外，缓冲区域可以有效地代替铝作为末端金属活性区域。

公开(公告)号：US09159610B2

公开(公告)日：2015-10-13

申请号：US14061319

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Moosung Chae ,  Larry Zhao

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.

Abstract translation: 一种用于制造集成电路的方法包括提供覆盖半导体衬底的导电材料和覆盖导电材料的电介质材料，其中开口暴露导电材料的表面和电介质材料的侧壁，并选择性地沉积第一层 导电材料的表面上的阻挡材料，其中电介质材料的侧壁保持暴露，第一阻挡材料使得如果在退火过程中退火，则第一阻挡材料将扩散到导电材料中。 该方法还包括修改暴露表面上的第一阻挡材料以形成第二阻挡材料，第二阻挡材料使得在退火过程期间，第二阻挡材料不会扩散到导电材料中并沉积第二阻挡层 沿着开口的侧壁的第一阻挡材料。 此外，该方法包括退火半导体衬底。 还公开了根据前述方法制造的集成电路。

公开(公告)号：US09166588B2

公开(公告)日：2015-10-20

申请号：US14158917

申请日：2014-01-20

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC: H01L29/76 ,  H03K19/003 ,  H01L21/31 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/266 ,  H01L23/58

CPC classification number: H03K19/00315 ,  H01L21/26513 ,  H01L21/823425 ,  H01L21/823493 ,  H01L23/544 ,  H01L23/57 ,  H01L27/0203 ,  H01L27/088 ,  H01L2223/54413 ,  H01L2223/5444 ,  H01L2924/0002 ,  H04L9/3278 ,  H01L2924/00

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底和在半导体衬底中形成的阱。 阱包括具有第一离子浓度的第一区域和具有小于第一浓度的第二浓度的至少一个第二区域。 在井上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

公开(公告)号：US09659785B2

公开(公告)日：2017-05-23

申请号：US14841951

申请日：2015-09-01

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L21/31 ,  H01L21/306 ,  H01L21/324 ,  H01L21/3065 ,  H01L29/16

CPC classification number: H01L21/3086 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/324 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.