公开(公告)号：US12125540B2

公开(公告)日：2024-10-22

申请号：US17733474

申请日：2022-04-29

申请人： Micron Technology, Inc.

发明人： Mattia Robustelli ,  Innocenzo Tortorelli

IPC分类号： G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

CPC分类号： G11C16/102 ,  G11C16/22 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3404

摘要： Methods, systems, and devices for improving write latency and energy using asymmetric cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.

公开(公告)号：US12068038B2

公开(公告)日：2024-08-20

申请号：US17960018

申请日：2022-10-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Lien Linus Lu

IPC分类号： G11C16/22 ,  G06F12/14 ,  H04L9/32

CPC分类号： G11C16/22 ,  G06F12/1408 ,  H04L9/3278

摘要： Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a testing method for physical unclonable function (PUF) generator includes: verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array; determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states; when the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map; when the second number of second bit cells is determined to be zero, determining a third number of third bit cells, wherein the third bit cells are stable in the first map and stable in the second map; and when the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator.

公开(公告)号：US12008235B2

公开(公告)日：2024-06-11

申请号：US18336316

申请日：2023-06-16

申请人： Silicon Motion, Inc.

发明人： Te-Kai Wang ,  Yu-Da Chen

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26

CPC分类号： G06F3/0605 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0679 ,  G06F12/0246 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G06F2212/72 ,  G06F2212/7206 ,  G06F2212/7207 ,  G06F2212/7209

摘要： A data storage device with flash memory. The controller receives a mode selection command from a host. In response to the mode selection command, the controller sends a ready-to-transfer message to the host, to further receive a data out message from the host that is sent by the host in response to the ready-to-transfer message. The ready-to-transfer message and the data out message are UFS protocol information unit (UPIU) messages. The data out message is arranged to rewrite a first mode page setting among a plurality of mode page settings of firmware stored in the flash memory. In response to the data out message, the controller determines whether the data out message will change mode parameters which cannot be rewritten in the first mode page setting, to adopt or refuse new mode parameters issued through the data out message for the first mode page setting.

公开(公告)号：US20240145017A1

公开(公告)日：2024-05-02

申请号：US18364126

申请日：2023-08-02

申请人： Samsung Electronics Co., Ltd.

发明人： Dae Sik HAM ,  Yong-Wan SON ,  Sang-Hyun JOO

IPC分类号： G11C16/34 ,  G11C16/16 ,  G11C16/22

CPC分类号： G11C16/3495 ,  G11C16/16 ,  G11C16/22

摘要： Disclosed is a memory device which a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.

公开(公告)号：US20240071516A1

公开(公告)日：2024-02-29

申请号：US17897448

申请日：2022-08-29

申请人： MICRON TECHNOLOGY, INC.

发明人： Kenneth W. Marr ,  James E. Davis ,  Chiara Cerafogli

IPC分类号： G11C16/22 ,  G11C16/04 ,  G11C16/16

CPC分类号： G11C16/22 ,  G11C16/0483 ,  G11C16/16

摘要： A discharge circuit includes a transistor and a metal resistor connected to the transistor. The transistor includes a plurality of unit cells. The metal resistor includes a plurality of resistor portions corresponding to the plurality of unit cells. Each unit cell of the plurality of unit cells has a footprint and a corresponding resistor portion of the plurality of resistor portions is arranged within the footprint.

公开(公告)号：US11862245B2

公开(公告)日：2024-01-02

申请号：US17960441

申请日：2022-10-05

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C11/34 ,  G11C14/00 ,  H01L21/28 ,  G11C11/404 ,  G11C16/04 ,  H01L27/105 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B12/00 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40 ,  G11C16/22 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC分类号： G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  H01L27/105 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7841 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923 ,  H10B12/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/1203 ,  H10B12/056 ,  H10B12/36

摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

公开(公告)号：US20230393994A1

公开(公告)日：2023-12-07

申请号：US17814395

申请日：2022-07-22

申请人： Micron Technology, Inc.

发明人： Jeremy BINFET ,  Lance Walker DOVER ,  Tommaso VALI ,  Walter DI FRANCESCO

IPC分类号： G06F12/14 ,  G11C16/22

CPC分类号： G06F12/1466 ,  G11C16/22 ,  G11C16/0483

摘要： In some implementations, a memory device may resolve a set of latches of a NAND page buffer to a set of initialized values. The memory device may obtain a NAND page buffer initialized data set from the set of initialized values of the set of latches. The memory device may generate a security key using the NAND page buffer initialized data set.

公开(公告)号：US11810622B2

公开(公告)日：2023-11-07

申请号：US17677332

申请日：2022-02-22

申请人： Micron Technology, Inc.

发明人： Christopher J. Bueb ,  Aravind Ramamoorthy

IPC分类号： G11C16/04 ,  G11C16/22 ,  G11C11/56 ,  G11C16/26 ,  G11C16/10

CPC分类号： G11C16/22 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

摘要： Respective values of a subset of the plurality of memory cells of a memory device are compared to a pattern of pre-programmed memory cells. The pattern pre-programmed memory cells comprise representations of values of the pattern of pre-programmed memory cells when a temperature criterion is satisfied. Responsive to determining that at least a threshold number of the respective values of the subset matches the pattern of pre-programmed memory cells, a temperature reading from a thermal sensor coupled to the memory device is identified. Responsive to determining that the temperature reading does not correspond to a temperature criterion, determining that the thermal sensor has failed.

公开(公告)号：US11775199B2

公开(公告)日：2023-10-03

申请号：US17153519

申请日：2021-01-20

申请人： Micron Technology, Inc.

发明人： Fuad Badrieh

IPC分类号： G11C11/4074 ,  G06F3/06 ,  G11C5/14 ,  G11C11/22 ,  G11C16/22

CPC分类号： G06F3/0653 ,  G06F3/0625 ,  G06F3/0679 ,  G11C5/143 ,  G11C11/225 ,  G11C16/225

摘要： A voltage of a conductive line, such as a control line, a data line, or a voltage supply line associated with a memory die may be monitored. A frequency response of the voltage may be analyzed to determine if the conductive line may be operating at or near a specific frequency, such as a resonance frequency. If the conductive line is operating at or near the specific frequency, an action, such as a memory operation, may be performed to mitigate the resonance of the conductive line. The monitoring, analyzing, and action performing may be accomplished with circuitry of the memory die.

公开(公告)号：US11720249B2

公开(公告)日：2023-08-08

申请号：US18062075

申请日：2022-12-06

申请人： Silicon Motion, Inc.

发明人： Te-Kai Wang ,  Yu-Da Chen

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G11C16/22 ,  G11C16/10 ,  G11C16/26

CPC分类号： G06F3/0605 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0679 ,  G06F12/0246 ,  G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G06F2212/72 ,  G06F2212/7206 ,  G06F2212/7207 ,  G06F2212/7209

摘要： A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware that includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings. When determining, based on a reference array, that the data out message will change the mode parameters which cannot be rewritten in the first mode page setting, the controller rejects to change the mode parameters which cannot be rewritten in the first mode page setting. The reference array stores a rewriteable setting for each bit of the first mode page setting.