公开(公告)号：US20210383883A1

公开(公告)日：2021-12-09

申请号：US17154576

申请日：2021-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Chia-En HUANG ,  Yih WANG

IPC: G11C17/16 ,  G11C17/06 ,  G11C17/12 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A memory circuit includes a first programming device, a first circuit branch and a second circuit branch. The first programming device includes a first control terminal coupled to a first word line, and a first connecting end. The first circuit branch includes a first diode, and a first fuse element coupled to the first diode. The second circuit branch includes a second diode, and a second fuse element coupled to the second diode. The first circuit branch and the second circuit branch are coupled to the first connecting end of the first programming device.

公开(公告)号：US10388568B2

公开(公告)日：2019-08-20

申请号：US15950169

申请日：2018-04-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L25/065 ,  H01L21/683 ,  H01L29/786 ,  H01L29/78 ,  H01L21/84 ,  G11C29/00 ,  G11C17/06 ,  G11C16/04 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L21/762 ,  H01L23/544 ,  H01L23/36 ,  G11C17/14 ,  H01L21/8238 ,  G11C5/02 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11578 ,  H03K19/00 ,  G11C13/00 ,  H01L23/00 ,  H01L23/525 ,  H01L23/48 ,  H01L27/24 ,  G11C29/02 ,  G11C8/10 ,  H01L23/367 ,  H01L23/498 ,  G11C17/16

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.

公开(公告)号：US20190148234A1

公开(公告)日：2019-05-16

申请号：US16228757

申请日：2018-12-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L21/8238 ,  G11C17/14 ,  H01L21/683 ,  H01L29/786 ,  H01L29/78 ,  H01L21/84 ,  G11C29/00 ,  G11C17/06 ,  G11C16/04 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L21/762 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36

Abstract: A method for producing a 3D memory device including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form memory cells within the second level and within the third level, each of the first memory cells include one first transistor, each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, the memory is NAND, the first level includes memory peripheral circuits, at least one of the first memory cells is at least partially atop a portion of the peripheral circuits.

公开(公告)号：US10217667B2

公开(公告)日：2019-02-26

申请号：US15904347

申请日：2018-02-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/822 ,  H01L25/065 ,  H01L21/683 ,  H01L29/786 ,  H01L29/78 ,  H01L21/84 ,  G11C29/00 ,  G11C17/06 ,  G11C16/04 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L27/118 ,  H01L27/112 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L21/762 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  G11C17/14 ,  H01L21/8238 ,  H01L27/11 ,  H01L23/00 ,  H01L23/48

Abstract: A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.

公开(公告)号：US20170084348A1

公开(公告)日：2017-03-23

申请号：US15371127

申请日：2016-12-06

Applicant: Guobiao ZHANG

Inventor： Guobiao ZHANG

IPC: G11C17/18 ,  G11C17/06 ,  G11C17/16 ,  H01L27/112 ,  H01L27/102

CPC classification number: G11C5/02 ,  G11C8/06 ,  G11C11/56 ,  G11C17/00 ,  G11C17/06 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/71 ,  H01L21/8221 ,  H01L21/8229 ,  H01L25/0657 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/1128 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention discloses a three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.

公开(公告)号：US09361995B1

公开(公告)日：2016-06-07

申请号：US14602262

申请日：2015-01-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C17/06 ,  G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C8/08 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/04 ,  H01L27/11521

Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

公开(公告)号：US09087588B2

公开(公告)日：2015-07-21

申请号：US13595426

申请日：2012-08-27

Applicant: Euipil Kwon

Inventor： Euipil Kwon

IPC: G11C17/06 ,  G11C17/18 ,  H01L27/10 ,  H01L27/102

CPC classification number: G11C17/06 ,  G11C17/18 ,  H01L27/101 ,  H01L27/1021

Abstract: A programmable non-volatile memory including a memory cell includes a transistor acting as an anti-fuse and two diodes for access. The memory cell that can store two bits and includes a transistor acting as an anti-fuse and two diodes for access, wherein the cell transistor includes: the source electrode formed by a metal; the first diode as the source region contact structure; the drain electrode formed by a metal; and the second diode as the drain region contact structure wherein the cell transistor, the oxide layer between the source area and the gate is the first anti-fuse the first storage; the oxide layer between the drain area and the gate is the second anti-fuse the second storage; the two diodes are connected in series to access the two anti-fuses.

Abstract translation: 包括存储单元的可编程非易失性存储器包括用作反熔丝的晶体管和用于存取的两个二极管。 存储单元，其可以存储两位，并且包括用作反熔丝的晶体管和用于存取的两个二极管，其中所述单元晶体管包括：由金属形成的源电极; 第一个二极管作为源区接触结构; 由金属形成的漏电极; 并且所述第二二极管作为漏区接触结构，其中所述单元晶体管，所述源极区和所述栅极之间的氧化物层是所述第一存储器的第一反熔丝; 漏极区域和栅极之间的氧化层是第二个保险丝的第二个保险丝; 两个二极管串联连接以访问两个防熔断器。

公开(公告)号：US09007805B2

公开(公告)日：2015-04-14

申请号：US14042608

申请日：2013-09-30

Applicant: Broadcom Corporation

Inventor： Yong Lu ,  Roy Milton Carlson

IPC: G11C17/06 ,  H01L27/112

CPC classification number: G11C17/06 ,  H01L27/11206

Abstract: A device for one-time-programmable (OTP) memory may include a capacitor formed by a conductive layer, an oxide layer, and a semiconductor well, and a diode that is formed after programing the device. The device may be programmable by applying a voltage between the conductive layer and the semiconductor well. The applied voltage may be capable of rupturing the oxide layer at one or more points. The conductive layer, the oxide layer, and the semiconductor well may be native CMOS process formations.

Abstract translation: 用于一次可编程（OTP）存储器的器件可以包括由导电层，氧化物层和半导体阱形成的电容器，以及在对器件编程之后形成的二极管。 该器件可以通过在导电层和半导体阱之间施加电压来编程。 施加的电压可能能够在一个或多个点破坏氧化物层。 导电层，氧化物层和半导体阱可以是天然CMOS工艺制造。

公开(公告)号：US08913415B2

公开(公告)日：2014-12-16

申请号：US13835308

申请日：2013-03-15

Applicant: Shine C. Chung

Inventor： Shine C. Chung

IPC: G11C17/16 ,  G11C17/06 ,  G11C17/14 ,  H01L43/08 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC classification number: G11C17/06 ,  G11C17/14 ,  H01L27/224 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof.

Abstract translation: 以标准CMOS逻辑工艺制造的结二极管可用作一次性可编程（OTP）器件的程序选择器，例如电熔丝，接触/通孔保险丝，接触/通孔抗熔丝或栅极氧化物击穿反熔丝， OTP器件具有至少一个耦合到存储器单元中的至少一个二极管的OTP元件。 二极管可以由CMOS N阱中的P +和N +有源区域或作为二极管的P和N端子的隔离有源区域构成。 可以通过虚拟MOS栅极，SBL或STI / LOCOS隔离来提供单元中或单元之间的二极管的P +与N +有源区之间的隔离。 OTP元件可以是多晶硅，硅化多晶硅，硅化物，金属，金属合金，局部互连，热隔离有源区，CMOS栅极或其组合。

公开(公告)号：US08546898B2

公开(公告)日：2013-10-01

申请号：US13259196

申请日：2009-09-29

Applicant: Lars Thylen ,  Alexandre Bratkovski ,  Shih-Yuan Wang ,  R. Stanley Williams

Inventor： Lars Thylen ,  Alexandre Bratkovski ,  Shih-Yuan Wang ,  R. Stanley Williams

IPC: H01L27/14 ,  G11C19/08 ,  G11C17/06 ,  G11C11/00

CPC classification number: H01L27/14609 ,  G11C7/005 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/047 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/77 ,  H01L27/14621 ,  H01L27/307

Abstract: An optoelectronic memory cell has a transparent top electrode, a photoactive layer, a latching layer, and a bottom electrode. The photoactive layer absorbs photons transmitted through the top electrode and generates charge carriers. During light exposure, the latching layer changes its resistance under an applied electric field in response to the generation of charge carriers in the photoactive layer.

Abstract translation: 光电存储单元具有透明的顶电极，光敏层，闭锁层和底电极。 光活性层吸收通过顶部电极传输的光子并产生电荷载体。 在曝光期间，响应于光活性层中的电荷载体的产生，锁存层在施加的电场下改变其电阻。