公开(公告)号：WO2008057895A1

公开(公告)日：2008-05-15

申请号：PCT/US2007/083246

申请日：2007-10-31

Applicant: ATMEL CORPORATION ,  LAM, Ken, M.

Inventor： LAM, Ken, M.

IPC: H01L23/02

CPC classification number: H05K1/185 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H05K3/4602 ,  H05K2203/0165 ,  H05K2203/085 ,  H05K2203/1469 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic multi -component package (74, 75) is assembled by placing multiple electronic components (30) within multiple openings (16) of a package substrate (12), then depositing and curing adhesive filler (34) in gaps between the components and the inner peripheries of the openings. Circuit features (38, 42), including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces (22F, 22B) of the package substrate. Preformed conductive vias (18) through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components (50, 54, 58) may be attached (52, 56, 60) to conductive lands on at least one side of the package. The circuit features also include contact pads (66) for external package connections, such as in a ball-grid-array or equivalent structure.

Abstract translation: 通过将多个电子组件（30）放置在封装衬底（12）的多个开口（16）内来组装电子多组件封装（74,75），然后沉积并固化粘合剂填充物（ 34）在部件和开口的内周之间的间隙中。 通过薄膜光刻在封装衬底的正面和背面（22F，22B）上形成包括导电互连的电路特征（38,42）。 通过封装衬底的预成型导电通孔（18）提供了在相对衬底表面上的电路特征之间的电连接。 额外的电子组件（50,54,58）可以被附接到（52,56,60）至包装的至少一侧上的导电区。 电路特征还包括用于外部封装连接的接触垫（66），例如球栅阵列或等效结构。

公开(公告)号：WO2010102229A1

公开(公告)日：2010-09-10

申请号：PCT/US2010/026394

申请日：2010-03-05

Applicant: ATMEL CORPORATION ,  LAM, Ken, M.

Inventor： LAM, Ken, M.

IPC: H01L21/68 ,  H01L21/60 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/552 ,  H01L23/08

CPC classification number: H01L21/6835 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83855 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit assembly comprises an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer. An overfill material encapsulates at least the integrated circuit die and the plurality of wire bonds, and a plurality of solder balls are formed on the plurality of external connection pads.

Abstract translation: 集成电路组件包括集成电路管芯和可布置的金属层，其包括将多个引线接合焊盘连接到多个外部连接焊盘的金属迹线，使得金属迹线可在管芯区域下布置。 非导电粘合剂层将集成电路管芯耦合到可路由的金属层，并且多个引线将集成电路管芯上的引线接合电路连接到可布线金属层中的引线接合焊盘。 至少封装了集成电路管芯和多个引线接合的填充材料，并且在多个外部连接焊盘上形成多个焊球。

公开(公告)号：WO2008057896A2

公开(公告)日：2008-05-15

申请号：PCT/US2007/083251

申请日：2007-10-31

Applicant: ATMEL CORPORATION ,  LAM, Ken, M.

Inventor： LAM, Ken, M.

IPC: B23P19/04 ,  H01L21/027 ,  H05K7/02

CPC classification number: H05K1/185 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H05K3/4602 ,  H05K2203/0165 ,  H05K2203/085 ,  H05K2203/1469 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic multi -component package (74, 75) is assembled by placing multiple electronic components (30) within multiple openings (16) of a package substrate (12), then depositing and curing adhesive filler (34) in gaps between the components and the inner peripheries of the openings. Circuit features (38, 42), including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces (22F, 22B) of the package substrate. Preformed conductive vias (18) through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components (50, 54, 58) may be attached (52, 56, 60) to conductive lands on at least one side of the package. The circuit features also include contact pads (66) for external package connections, such as in a ball-grid-array or equivalent structure.

公开(公告)号：WO2008008587A2

公开(公告)日：2008-01-17

申请号：PCT/US2007071079

申请日：2007-06-13

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L23/02

CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73257 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and a method for producing three- dimensional integrated circuit packages. In one embodiment, an electronics package (200) with at least two dice (207, 209) are stacked one atop another is disclosed. A top die (209) is of smaller size compared with a bottom die (207) such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die (207) contains contact pads (211) on the front side that couple with one or more passive components (213) fabricated on the back side of the top die (209) to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Abstract translation: 一种用于生产三维集成电路封装的装置和方法。 在一个实施例中，公开了具有至少两个骰子（207,209）的电子封装（200）。 与底模（207）相比，顶模（209）尺寸较小，使得在芯片附接操作之后，底模的引线接合焊盘将被暴露以用于随后的引线接合操作。 底模（207）包括在前侧上的与在顶模（209）的背面上制造的一个或多个无源元件（213）耦合以便完成电路的接触焊盘（211）。 在另一个示例性实施例中，公开了一种在堆叠管芯封装中形成一个或多个三维无源部件的方法，其中部分电感器元件制造在底模的前侧和顶模的背面。 顶部和底部元件联接在一起，完成无源部件。

公开(公告)号：WO2008008586A2

公开(公告)日：2008-01-17

申请号：PCT/US2007/070994

申请日：2007-06-12

Applicant: ATMEL CORPORATION ,  LAM, Ken, M.

Inventor： LAM, Ken, M.

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29355 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An apparatus and a method for packaging semiconductor devices (205, 207). Disclosed are multi- die packaging apparatuses (200) and techniques, especially useful for integrated circuit dice (207) involving insulative substrates (225), such as silicon- on-insulator (SOI), where grounding of a base layer (225) is not reasonably practical. Disclosed is a means for effectively grounding all layers of an integrated circuit device (205, 207) regardless of whether the device (205, 207) makes direct contact with a die-attach paddle (201).

Abstract translation: 一种用于封装半导体器件（205,207）的装置和方法。 公开了一种多芯片封装装置（200）和技术，其特别适用于涉及绝缘基板（225）的集成电路晶片（207），绝缘体绝缘体（SOI），其中基极层（225）的接地为 不合理实用。 公开了一种用于有效地接地集成电路装置（205,207）的所有层的装置，而不管装置（205,207）是否与芯片附着桨（201）直接接触。

公开(公告)号：WO2008008586A3

公开(公告)日：2008-05-02

申请号：PCT/US2007070994

申请日：2007-06-12

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29355 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An apparatus and a method for packaging semiconductor devices (205, 207). Disclosed are multi- die packaging apparatuses (200) and techniques, especially useful for integrated circuit dice (207) involving insulative substrates (225), such as silicon- on-insulator (SOI), where grounding of a base layer (225) is not reasonably practical. Disclosed is a means for effectively grounding all layers of an integrated circuit device (205, 207) regardless of whether the device (205, 207) makes direct contact with a die-attach paddle (201).

Abstract translation: 一种封装半导体器件的装置和方法（205,207）。 公开了多芯片封装装置（200）和技术，尤其可用于涉及绝缘衬底（225）的绝缘衬底（225）（例如绝缘体上硅（SOI））的集成电路裸片（207），其中基底层 不合理实际。 公开了一种用于有效地将集成电路器件（205,207）的所有层接地的装置，而不管器件（205,207）是否与管芯附接板（201）直接接触。

公开(公告)号：WO2008008587A3

公开(公告)日：2008-01-17

申请号：PCT/US2007/071079

申请日：2007-06-13

Applicant: ATMEL CORPORATION ,  LAM, Ken, M.

Inventor： LAM, Ken, M.

IPC: H01L23/50 ,  H01L23/485 ,  H01L23/538 ,  H01L23/12 ,  H01L23/522

Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package (200) with at least two dice (207, 209) are stacked one atop another is disclosed. A top die (209) is of smaller size compared with a bottom die (207) such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die (207) contains contact pads (211) on the front side that couple with one or more passive components (213) fabricated on the back side of the top die (209) to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

公开(公告)号：WO2008008581A3

公开(公告)日：2008-01-17

申请号：PCT/US2007/070612

申请日：2007-06-07

Applicant: ATMEL CORPORATION ,  LAM, Ken, M.

Inventor： LAM, Ken, M.

IPC: H01L29/00 ,  H01L23/34 ,  H01L21/44 ,  H01L21/8222

Abstract: An apparatus and a method for producing passive components on an integrated circuit device (100). The integrated circuit device (100) has post wafer fabrication integrated passive components (107) situated on the opposite substrate side (105) of the device's integrated circuitry (103). Electrical contact pads (109) of the passive components (107) are configured to be coupled to the electronics package contact pads to complete the electronic package.

公开(公告)号：WO2007127739A3

公开(公告)日：2007-11-08

申请号：PCT/US2007/067315

申请日：2007-04-24

Applicant: ATMEL CORPORATION ,  LAM, Ken, M.

Inventor： LAM, Ken, M.

IPC: H01L23/02 ,  H01L23/04 ,  H01L23/48 ,  H01L23/40 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44

Abstract: An apparatus and a method for packaging semi-conductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels (213) formed through an encapsulation area (215) surrounding the device (207) and associated bond wires (211) are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads (205) to an uppermost portion of the encapsulated area (215) . The sacrificial metal base strip (201) serves as a plating bus and is etch-removed after plating. The filled tunnels (213) allow components to be stacked in a three-dimensional configuration.

公开(公告)号：WO2007127739A2

公开(公告)日：2007-11-08

申请号：PCT/US2007067315

申请日：2007-04-24

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49146 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and a method for packaging semi-conductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels (213) formed through an encapsulation area (215) surrounding the device (207) and associated bond wires (211) are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads (205) to an uppermost portion of the encapsulated area (215) . The sacrificial metal base strip (201) serves as a plating bus and is etch-removed after plating. The filled tunnels (213) allow components to be stacked in a three-dimensional configuration.

Abstract translation: 一种用于封装半导体器件的装置和方法。 该设备适用于许多类型的使用牺牲金属基底条的当代包装方案。 通过围绕设备（207）和相关联的接合线（211）的封装区域（215）形成的隧道（213）通过例如电镀被金属导体填充，并将底部接触焊盘（205）延伸到最上部 的封装区域（215）。 牺牲金属基带（201）用作电镀母线，并且在电镀之后被蚀刻去除。 填充的隧道（213）允许组件以三维配置堆叠。