公开(公告)号：WO2005027192A2

公开(公告)日：2005-03-24

申请号：PCT/US2004/028163

申请日：2004-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DOKUMACI, Omer ,  CHEN, Huajie ,  CHIDAMBARRAO, Dureseti ,  YANG, Haining, S.

Inventor： DOKUMACI, Omer ,  CHEN, Huajie ,  CHIDAMBARRAO, Dureseti ,  YANG, Haining, S.

IPC: H01L

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract translation: 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

公开(公告)号：WO2005013344A1

公开(公告)日：2005-02-10

申请号：PCT/EP2004/051588

申请日：2004-07-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  LEE, Kam-Leung ,  ZHU, Huilong

Inventor： LEE, Kam-Leung ,  ZHU, Huilong

IPC: H01L21/265

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/1054

Abstract: A method (and resulting structure) of forming a semiconductor device, includes implanting, on, a substrate, a dopant and at least one species, annealing the substrate, the at least one species retarding a diffusion of the dopant during the annealing of the substrate.

Abstract translation: 形成半导体器件的方法（和结果）包括在衬底上注入掺杂剂和至少一种物质，退火衬底，所述至少一种物质在衬底的退火期间延迟掺杂剂的扩散 。

公开(公告)号：WO2004021429B1

公开(公告)日：2004-07-08

申请号：PCT/US0326815

申请日：2003-08-28

Applicant: MICRON TECHNOLOGY INC

Inventor： JUENGLING WERNER ,  LANE RICHARD H

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L21/28052 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer (201), a conducting layer (202), and a first insulating layer (203). Sidewall spacers (209a, 209b) are formed adjacent to the sides of the gate stack structure and a third insulating layer (211) is formed over the gate stack and substrate. The third insulating layer (211) and first insulating layer (203) are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.

Abstract translation: 本发明教导了一种形成具有硅化物栅的MOSFET晶体管的方法，其在形成栅极堆叠结构时不会产生通过蚀刻含金属层产生的问题。 在包括栅极氧化物层（201），导电层（202）和第一绝缘层（203）的半导体衬底之上形成栅堆叠。 侧壁间隔物（209a，209b）与栅极堆叠结构的侧面相邻地形成，并且在栅极堆叠和衬底上形成第三绝缘层（211）。 去除第三绝缘层（211）和第一绝缘层（203）以暴露导电层，并且至少一个未蚀刻的含金属层形成在导电层上并与导电层接触。 然后，栅极堆叠结构经历不同变化的硅化处理，最终形成硅化物栅极。

公开(公告)号：WO2004021429A1

公开(公告)日：2004-03-11

申请号：PCT/US2003/026815

申请日：2003-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JUENGLING, Werner ,  LANE, Richard, H.

IPC: H01L21/336

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L21/28052 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer (201), a conducting layer (202), and a first insulating layer (203). Sidewall spacers (209a, 209b) are formed adjacent to the sides of the gate stack structure and a third insulating layer (211) is formed over the gate stack and substrate. The third insulating layer (211) and first insulating layer (203) are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.

Abstract translation: 本发明教导了一种形成具有硅化物栅极的MOSFET晶体管的方法，所述硅化物栅极在形成栅极堆叠结构时不会受到通过蚀刻含金属层产生的问题的影响。 栅极叠层形成在包括栅极氧化物层（201），导电层（202）和第一绝缘层（203）的半导体衬底之上。 在栅叠层结构的侧面附近形成侧壁间隔物（209a，209b），并且在栅叠层和衬底上形成第三绝缘层（211）。 去除第三绝缘层（211）和第一绝缘层（203）以暴露导电层，并且在导电层上方并且与导电层接触形成至少一个未被蚀刻的含金属层。 然后，栅极堆叠结构经历具有不同变化的硅化工艺，以最终形成硅化物栅极。

公开(公告)号：WO2019005109A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040306

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： RADOSAVLJEVIC, Marko ,  THEN, Han Wui ,  DASGUPTA, Sansaptak

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/764

CPC classification number: H01L21/764 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575

Abstract: An integrated circuit transistor may be fabricated having a reinforced airgap spacer formed as a gate sidewall spacer, such that the reinforced airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the integrated circuit transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the reinforced airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the integrated circuit transistor.

公开(公告)号：WO2017003407A1

公开(公告)日：2017-01-05

申请号：PCT/US2015/038190

申请日：2015-06-27

Applicant: INTEL CORPORATION

Inventor： RACHMADY, Willy ,  METZ, Matthew V. ,  LE, Van H. ,  KAVALIEROS, Jack T. ,  GARDNER, Sanaz K.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/6681 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/30612 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7853

Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.

Abstract translation: 一种包括三维半导体本体的装置，包括沟道区和设置在沟道区的相对侧的结区，所述三维半导体本体包括多个纳米线，所述多个纳米线包括设置在通过所述接合区域分离的各个平面中的锗材料， 第二材料，其中所述第二材料的晶格常数类似于所述锗材料的晶格常数; 以及设置在所述沟道区上的栅极堆叠，所述栅极堆叠包括设置在栅极电介质上的栅电极。 一种包括在衬底上的分离平面中形成多个纳米线的方法，所述多个纳米线中的每一个包括锗材料并通过牺牲材料与相邻的纳米线分离; 在指定的沟道区域中的多个纳米线上设置栅极堆叠，所述栅极堆叠包括电介质材料和栅电极。

公开(公告)号：WO2016191407A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/033876

申请日：2016-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： BAO, Junjing ,  YANG, Haining ,  LIU, Yanxiang ,  XU, Jeffrey Junhao

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract translation: 在导体的上表面上生长牺牲帽。 电介质隔离物抵靠导体的一侧。 在绝缘帽的侧壁上形成上绝缘侧绝缘体。 牺牲帽被选择性地蚀刻，留下盖子凹槽，并且上电介质侧隔离物面向盖凹槽。 氮化硅填充在盖凹部中，以形成中心帽和具有中心帽和上部电介质间隔物的保护帽。

公开(公告)号：WO2016039935A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/045393

申请日：2015-08-14

Applicant: APPLIED MATERIALS, INC.

Inventor： YIEH, Ellie Y. ,  GODET, Ludovic ,  XUE, Jun ,  NEMANI, Srinivas D. ,  LI, DongQing (Karen) ,  CHEN, Erica

IPC: H01L21/205 ,  H01L21/31

CPC classification number: H01L21/26506 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31155 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Species are supplied to a flowable layer over a substrate. A property of the flowable layer is modified by implanting the species to the flowable layer. The property comprises a density, a stress, a film shrinkage, an etch selectivity, or any combination thereof.

Abstract translation: 物质被提供到基底上的可流动层。 可流动层的性质通过将物种注入可流动层来改变。 该性质包括密度，应力，薄膜收缩率，蚀刻选择性或其任何组合。

公开(公告)号：WO2015112404A1

公开(公告)日：2015-07-30

申请号：PCT/US2015/011481

申请日：2015-01-14

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： LEE, Donovan ,  PURAYATH, Vinod R. ,  KAI, James

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L27/11517 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42324 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7881

Abstract: Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid.

Abstract translation: 悬浮电荷存储区域用于非易失性存储以减少寄生干扰并增加存储器件中的电荷保持。 电荷存储区域从覆盖的中间介电材料悬浮。 电荷存储区域包括在行和列方向上延伸的上表面和下表面。 电荷存储区域的上表面与上覆的中间介电材料耦合。 下表面面向基板表面，并通过空隙与基板表面分离。 电荷存储区包括在列方向上延伸的第一垂直侧壁和第二垂直侧壁以及沿行方向延伸的第三垂直侧壁和第四垂直侧壁。 第一，第二，第三和第四垂直侧壁通过空隙与非易失性存储器的相邻特征分离。 空隙可以包括真空，空气，气体或液体。

公开(公告)号：WO2015078104A1

公开(公告)日：2015-06-04

申请号：PCT/CN2014/070713

申请日：2014-01-16

Applicant: 中国科学院微电子研究所

Inventor： 朱慧珑

IPC: H01L21/336

CPC classification number: H01L29/6681 ,  H01L21/26506 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: 提供了一种半导体装置及其制造方法。一示例装置可以包括：体半导体衬底；在衬底上形成的鰭；在衬底上形成的第一FinFET和第二FinFET，其中第一FinFET包括与所述鰭相交的第一栅堆叠以及位于第一栅堆叠侧壁上的第一栅侧墙，第二半导体器件包括与所述鰭相交的第二栅堆叠以及位于第二栅堆叠侧壁上的第二栅侧墙；在第一FinFET和第二FinFET之间形成与鰭相交的伪栅侧墙；自对准于伪栅侧墙所限定的空间的隔离部，所述隔离部将第一FinFET和第二FinFET电隔离；以及位于隔离部下方、与隔离部相接的绝缘层。