公开(公告)号：WO9716866A3

公开(公告)日：1997-06-19

申请号：PCT/US9608328

申请日：1996-05-28

Applicant: FORMFACTOR INC ,  KHANDROS IGOR Y ,  CHANG SUNG CHUL ,  SMITH WILLIAM D

Inventor： KHANDROS IGOR Y ,  CHANG SUNG CHUL ,  SMITH WILLIAM D

IPC: H01L21/60 ,  B23K20/00 ,  C23C18/16 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  H01L21/00 ,  H01L21/48 ,  H01L21/603 ,  H01L21/66 ,  H01L23/32 ,  H01L23/48 ,  H01L23/485 ,  H01L23/49 ,  H01L23/498 ,  H01L25/16 ,  H05K3/32 ,  H01R

CPC classification number: B23K20/004 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  H01L21/4853 ,  H01L21/4889 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/72 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/326 ,  H01L2924/00 ,  H01L2224/48

Abstract: A plurality of free-standing spring elements (512) are mounted to a surface (510a) of a carrier substrate (510). The carrier substrate (510) is mounted to a surface (502a) of a semiconductor device (502). Bond pads (504) of the semiconductor device are connected to the spring elements (512) by bond wires (520) extending between the bond pads (504) and terminals (516) associated with the spring elements. Alternatively, the carrier is flip-chip reflow soldered to the semiconductor device. The carrier substrate (510) is suitably mounted to one or more semiconductor devices (532, 534) prior to the semiconductor devices being singulated from a semiconductor wafer upon which they are formed. Resilience and compliance to effect pressure connections to the semiconductor device (502) are provided by the spring elements (512) extending from the carrier substrate (510), per se. Hence, the carrier substrate (510) suitably remains rigid with respect to the semiconductor device (502). The carrier substrate (510) is advantageously pre-fabricated, by mounting the spring elements (512) thereto prior to mounting the carrier substrate to the semiconductor device(s).

公开(公告)号：WO2023285046A2

公开(公告)日：2023-01-19

申请号：PCT/EP2022/065945

申请日：2022-06-13

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： KÜRTEN, Bernd ,  ZEYSS, Felix

IPC: H01L23/49 ,  H01L25/07

Abstract: Die Erfindung betrifft eine Halbleiteranordnung (2) mit einem Halbleiterelement (4), einem Substrat (6) und Bondverbindungsmitteln (20a, 20b, 20c, 34, 58). Um, im Vergleich zum Stand der Technik, eine verbesserte Verdrahtung zu erreichen, wird vorgeschlagen, dass das Halbleiterelement (4), insbesondere stoffschlüssig, mit dem Substrat (6) verbunden ist, wobei das Halbleiterelement (4) auf einer dem Substrat (6) abgewandten Seite zumindest eine Kontaktfläche (8) aufweist, wobei zumindest eine Kontaktfläche (8) des Halbleiterelements (4) über zumindest ein erstes Bondverbindungsmittel (20a, 20b, 20c) mit dem Substrat (6) verbunden ist, wobei das zumindest eine erste Bondverbindungsmittel (20a, 20b, 20c) auf der Kontaktfläche (8) jeweils zumindest einen ersten Steppkontakt (22a, 22b, 22c) ausbildet, welcher zwischen einem ersten Loop (24a, 24b, 24c) und einem zweiten Loop (26a, 26b, 26c) des jeweiligen ersten Bondverbindungsmittels (20a, 20b, 20c) angeordnet ist, wobei der erste Loop (24a, 24b, 24c) ein erstes Maximum (28a, 28b, 28c) und der zweite Loop (26a, 26b, 26c) ein zweites Maximum (30a, 30b, 30c) aufweist, wobei ein erster Quer-Loop (32) eines zweiten Bondverbindungsmittels (34) oberhalb des ersten Steppkontakts (22a, 22b, 22c) und, parallel zur Kontaktfläche (8) verlaufend betrachtet, zwischen dem ersten Maximum (28a, 28b, 28c) des ersten Loops (24a, 24b, 24c) und dem zweiten Maximum (30a, 30b, 30c) des zweiten Loops (26a, 26b, 26c) verlaufend angeordnet ist, wobei der erste Quer-Loop (32) des zweiten Bondverbindungsmittels (34), insbesondere vollständig, unterhalb des ersten Maximums (28a, 28b, 28c) des ersten Loops (24a, 24b, 24c) und/oder des zweiten Maximums (30a, 30b, 30c) des zweiten Loops (26a, 26b, 26c) verlaufend angeordnet ist.

公开(公告)号：WO2023280669A2

公开(公告)日：2023-01-12

申请号：PCT/EP2022/068021

申请日：2022-06-30

Applicant: HITACHI ENERGY SWITZERLAND AG

Inventor： YAGHOUBI, Farhad ,  ZHANG, Biwei ,  BEYER, Harald

IPC: H01L23/488 ,  H01L23/49 ,  H01L21/60 ,  H01L25/07

Abstract: A power module (10) is provided which comprises a substrate (2), an electronic component (3) and an electrical connection (4), wherein the power module further comprises a first connection layer (5B) and a second connection layer (5C). The substrate (2) has a first metallization layer (21) and a second metallization layer (22) spatially separated from the first metallization layer (21) by a separating trench (2T). The first connection layer (5B) is formed along a vertical direction between the substrate (2) and the electronic component (3). The electronic component (3) is a semiconductor chip and is electrically and thermally connected to the first metallization layer (21) by the first connection layer (5B) being a patterned sintered connection layer which forms a sintered connection between the substrate (2) and the electronic component (3). In top view, an area (50) of the sintered connection is partly covered by a sintering material, wherein not-covered subregions (50U) are bordered by one or several outer edges (50E) of the area (50). A ratio of surfaces of the not-covered subregions (50U) to the respective area (50) of the sintered connection is between 10 % and 75 %, inclusive. The electrical connection (4) is electrically connected to the electronic component (3) by the second connection layer (5C) being another patterned sintered connection layer. Moreover, a method for producing such a power module (10) is provided.

公开(公告)号：WO2023273594A1

公开(公告)日：2023-01-05

申请号：PCT/CN2022/090867

申请日：2022-05-05

Applicant: 颀中科技（苏州）有限公司 ,  合肥颀中科技股份有限公司

Inventor： 杨宗铭 ,  孙轶

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/49 ,  H01L2224/11

Abstract: 一种金属凸块结构，包括：裸芯片（10），具有基板（101）和设置在基板（101）上表面的焊盘（102）、钝化层（103）；绝缘垫高块（30），设置在焊盘（102）的边缘位置；金属凸块（20），设置在裸芯片（10）上，金属凸块（20）的底端形成有设置在焊盘（102）之上的中间部（203）和设置在绝缘垫高块（30）之上的绝缘垫高部（204）；金属凸块（20）的顶端形成有与中间部（203）位置相对的凹陷部（201）和与绝缘垫高部（204）位置相对的突起部（202）。该金属凸块结构能有效避免引脚熔融、外溢造成的相邻焊点之间短接的问题。

公开(公告)号：WO2023273099A1

公开(公告)日：2023-01-05

申请号：PCT/CN2021/130401

申请日：2021-11-12

Applicant: 中车株洲电力机车研究所有限公司

Inventor： 陈燕平 ,  窦泽春 ,  谢舜蒙 ,  彭勇殿 ,  朱武 ,  张荣 ,  荣春晖 ,  袁勇 ,  陈明翊 ,  谭一帆

IPC: H01L25/18 ,  H02H3/08 ,  G01R19/165 ,  G01R31/26 ,  G01R31/52 ,  H01L23/49

Abstract: 本发明提供了一种功率半导体器件。该功率半导体器件包括：至少一个晶体管元件，其中，所述晶体管元件包括高压功率端、低压功率端及控制端，所述高压功率端延伸出所述功率半导体器件的封装以构成所述功率半导体器件的高压引脚，所述低压功率端延伸出所述功率半导体器件的封装以构成所述功率半导体器件的低压引脚，所述控制端延伸出所述功率半导体器件的封装以构成所述功率半导体器件的控制引脚；以及至少一个检测二极管单元，其中，所述检测二极管单元的阴极连接所述至少一个晶体管元件的所述高压功率端，所述检测二极管单元的阳极延伸出所述功率半导体器件的封装以构成所述功率半导体器件的检测引脚。

公开(公告)号：WO2022209029A1

公开(公告)日：2022-10-06

申请号：PCT/JP2021/045431

申请日：2021-12-03

Applicant: MITSUBISHI ELECTRIC CORPORATION ,  MITSUBISHI ELECTRIC R&D CENTRE EUROPE B.V.

Inventor： PICHON, Pierre-Yves ,  BRANDELERO, Julio ,  OUHAB, Merouane ,  DEGRENNE, Nicolas

IPC: H01L21/607 ,  H01L23/49 ,  B23K20/00 ,  B23K20/004 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/056 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48458 ,  H01L2224/4851 ,  H01L2224/78315 ,  H01L2224/78901 ,  H01L2224/85205 ,  H01L2224/8593 ,  H01L2224/85947 ,  H01L2224/85948 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85

Abstract: The invention relates to producing a semiconductor chip-metal wire bond, by performing the steps of bonding a wire having a metal body to the semiconductor chip so as to connect the wire to the semiconductor chip, the bond metal having a polycrystalline microstructure, and deforming a bonding region of the metal body in contact with to the semiconductor chip, the deformed bonding region being characterized by a relative cross section area change given by (AA), where Af is a final cross section area and A0 is an initial cross section area, the deformation involving an increase of a dislocation density in the microstructure of at least a portion of the bonding region.

公开(公告)号：WO2022150348A1

公开(公告)日：2022-07-14

申请号：PCT/US2022/011261

申请日：2022-01-05

Applicant: CREE, INC.

Inventor： OREJOLA, Erwin ,  CONDIE, Brian ,  ANDRE, Ulf

IPC: H01L23/49 ,  H01L23/66

Abstract: A packaged semiconductor device includes a first bond pad (225), a second bond pad (165, 165'), a first bond wire that includes a first end bonded to the first bond pad (225) and a second end bonded to the second bond pad (165, 165'), and a second bond wire that includes a first end that is electrically connected to the first bond pad (225) and a second end that is electrically connected to the second bond pad (165, 165'). The first end of the second bond wire is bonded to the first end of the first bond wire. A method of bonding a bond wire includes bonding a first end of a first bond wire to a contact surface of a first bond pad (225) and bonding a first end of a second bond wire to a surface of the first end of the first bond wire.

公开(公告)号：WO2022010235A1

公开(公告)日：2022-01-13

申请号：PCT/KR2021/008600

申请日：2021-07-06

Applicant: 주식회사 프로텍

Inventor： 고윤성 ,  안근식

IPC: H01L23/00 ,  H01L23/49 ,  H01L23/492

Abstract: 본 발명은 가압식 구리 필러 기판 본딩 방법에 관한 것으로, 더욱 상세하게는 원기둥 형태의 구리 필러를 효과적으로 기판에 배치하여 고정밀도로 본딩하는 가압식 구리 필러 기판 본딩 방법에 관한 것이다. 본 발명의 가압식 구리 필러 기판 본딩 방법은 매우 작은 크기의 구리 필러를 기판에 탑재하는 공정을 정확하고 효과적으로 수행할 수 있는 효과가 있다.

公开(公告)号：WO2021022292A1

公开(公告)日：2021-02-04

申请号：PCT/US2020/070303

申请日：2020-07-22

Applicant: LAM RESEARCH CORPORATION

Inventor： BANIK II, Stephen, J. ,  BLICKENSDERFER, Jacob, Kurtis ,  VENKATRAMAN, Kailash ,  OBERST, Justin ,  CHUA, Lee, Peng ,  BUCKALEW, Bryan, L. ,  MAYER, Steven, T.

IPC: H01L23/00 ,  H01L23/49

Abstract: A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

公开(公告)号：WO2020160915A1

公开(公告)日：2020-08-13

申请号：PCT/EP2020/051558

申请日：2020-01-23

Applicant: JENOPTIK OPTICAL SYSTEMS GMBH

Inventor： DIENER, Romina ,  RISCHERT, Christian ,  SUESS, Katja ,  SEIDEL, Sebastian ,  ROELLIG, Ulrich

IPC: H01L21/60 ,  H01L23/49 ,  B23K35/26 ,  B23K35/40 ,  H01S5/022 ,  H01L33/62 ,  H01S5/024 ,  H01S5/40 ,  H01L23/373 ,  H01L23/427

Abstract: Die Erfindung betrifft ein Lötverfahren für ein Bauteil auf einen Träger (8). Dabei wird das Lot als Lotdraht (20) oder Lotbändchen (20) bereitgestellt und mit einem Ultraschallbonder auf eine Montage- oder Befestigungsfläche appliziert. Hernach wird das Bauteil auf dem Lot positioniert und das Lot aufgeschmolzen. Schließlich erstarrt das Lot unter Ausbildung einer Lötverbindung des Bauteils mit dem Träger (8).