公开(公告)号：WO2010078074A1

公开(公告)日：2010-07-08

申请号：PCT/US2009/068673

申请日：2009-12-18

Applicant: GLOBALFOUNDRIES INC. ,  LETZ, Tobias ,  FEUSTEL, Frank

Inventor： LETZ, Tobias ,  FEUSTEL, Frank

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886

Abstract: Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/ silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.

Abstract translation: 通过局部形成铜/硅化合物，可以在金属线和通孔之间的关键区域增强半导体器件复杂金属化系统中的电迁移行为。 在一些说明性实施例中，铜/硅化合物的形成可以与用于清洁暴露的表面区域和/或改变其分子结构的其它处理组合。

公开(公告)号：WO2010132277A1

公开(公告)日：2010-11-18

申请号：PCT/US2010/033948

申请日：2010-05-07

Applicant: GLOBALFOUNDRIES INC. ,  FEUSTEL, Frank ,  LETZ, Tobias ,  PREUSSE, Axel

Inventor： FEUSTEL, Frank ,  LETZ, Tobias ,  PREUSSE, Axel

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76867 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, the electromigration performance of copper metal lines at the top interface thereof may be enhanced by forming a copper alloy (132C) that is locally restricted to the interface (132S). To this end, an appropriate alloy-forming species, such as aluminum, may be provided on the basis of a non-masked deposition process and may be subsequently removed by a non-masked etch process, wherein the characteristic of the resulting alloy may be adjusted during an intermediate heat treatment.

Abstract translation: 在复杂的半导体器件中，通过形成局部限于界面（132S）的铜合金（132C）可以提高铜金属线在其顶部界面处的电迁移性能。 为此，可以在非掩蔽沉积工艺的基础上提供合适的合金形成物质，例如铝，然后通过非掩模蚀刻工艺除去，其中所得合金的特征可以是 在中间热处理期间调整。

公开(公告)号：WO2009045362A1

公开(公告)日：2009-04-09

申请号：PCT/US2008/011254

申请日：2008-09-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  FEUSTEL, Frank ,  LETZ, Tobias ,  PETERS, Carsten

Inventor： FEUSTEL, Frank ,  LETZ, Tobias ,  PETERS, Carsten

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure (300) comprises a semiconductor substrate (301). A layer of an electrically insulating material (304) is formed over the semiconductor substrate (301). An electrically conductive feature (312) is formed in the layer of electrically insulating material (304). A first layer of a semiconductor material (320) is formed between the electrically conductive feature (312) and the layer of electrically insulating material (304).

Abstract translation: 半导体结构（300）包括半导体衬底（301）。 在半导体衬底（301）上形成电绝缘材料层（304）。 导电特征（312）形成在电绝缘材料层（304）中。 在导电特征（312）和电绝缘材料层（304）之间形成第一半导体材料层（320）。

公开(公告)号：WO2010060639A1

公开(公告)日：2010-06-03

申请号：PCT/EP2009/008472

申请日：2009-11-27

Applicant: ADVANCED MICRO DEVICES INC ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG ,  WERNER, Thomas ,  FROHBERG, Kai ,  FEUSTEL, Frank

Inventor： WERNER, Thomas ,  FROHBERG, Kai ,  FEUSTEL, Frank

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Air gaps may be formed in a metallization layer of a microstructure device on the basis of a patterning sequence in which also respective via openings are formed. Thereafter, the via openings and the air gaps may be closed by a deposition process without significantly affecting the interior of the corresponding openings. Thereafter, the further processing may be continued by forming respective trenches while maintaining integrity of the covered air gaps. Thus, the relative permittivity of the interlayer dielectric material may efficiently be reduced without adding additional process complexity.

Abstract translation: 基于形成相应的通路孔的图案化顺序，可以在微结构器件的金属化层中形成气隙。 此后，通孔和气隙可以通过沉积工艺封闭，而不会明显地影响相应的开口的内部。 此后，可以通过在保持覆盖的气隙的完整性的同时形成相应的沟槽来继续进一步的处理。 因此，层间绝缘材料的相对介电常数可以有效地降低，而不增加额外的工艺复杂性。

公开(公告)号：WO2010097191A1

公开(公告)日：2010-09-02

申请号：PCT/EP2010/001092

申请日：2010-02-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  FEUSTEL, Frank ,  FROHBERG, Kai ,  WERNER, Thomas ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： FEUSTEL, Frank ,  FROHBERG, Kai ,  WERNER, Thomas

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: In a metallization system of a complex semiconductor device, metal pillars (271) such as copper pillars may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.

Abstract translation: 在复杂半导体器件的金属化系统中，诸如铜柱的金属柱（271）可以形成为钉状构造，以便减少作用在金属化系统上的最大机械应力，同时提供所需的接触表面用于连接到 封装衬底。 可以基于适当配置的抗蚀剂掩模获得钉状构造。

公开(公告)号：WO2008027471A1

公开(公告)日：2008-03-06

申请号：PCT/US2007/019071

申请日：2007-08-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  FROHBERG, Kai ,  FEUSTEL, Frank ,  WERNER, Thomas

Inventor： FROHBERG, Kai ,  FEUSTEL, Frank ,  WERNER, Thomas

IPC: H01L21/336

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor (100) may be significantly increased. For instance, non-conformal PECVD techniques may be used for forming highly stressed silicon nitride in a non-conformal manner, thereby achieving higher transistor performance for otherwise identical stress conditions. The transistor (100) comprises a gate electrode (106), sidewall spacers (107), source/drain regions (103) and stress inducing layer (110) formed above the gate electrode, spacers (107) and source/drain regions (103).

Abstract translation: 通过形成高度非保形的应力覆盖层，例如接触蚀刻停止层，可以显着增加对场效应晶体管（100）的各个沟道区域的应力传递的效率。 例如，非共形PECVD技术可以用于以非共形方式形成高应力氮化硅，从而在否则相同的应力条件下实现更高的晶体管性能。 晶体管（100）包括形成在栅电极上方的栅极（106），侧壁间隔物（107），源/漏区（103）和应力诱导层（110），间隔物（107）和源极/漏极区（103） ）。

公开(公告)号：WO2006130250A1

公开(公告)日：2006-12-07

申请号：PCT/US2006/014624

申请日：2006-04-19

Applicant: ADVANCED MICRO DEVICES, INC. ,  HUEBLER, Peter ,  KOSCHINSKY, Frank ,  FEUSTEL, Frank

Inventor： HUEBLER, Peter ,  KOSCHINSKY, Frank ,  FEUSTEL, Frank

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: By providing a stiffening layer (105) at three sidewalls (1055) of a trench (104) to be filled with a copper-containing metal, the reduced thermomechanical confinement of a low-k material (102) may be compensated for, at least to a certain degree, thereby reducing electromigration effects and hence increasing lifetime of sophisticated semiconductor devices having metallization layers including low-k dielectric materials (102) in combination with copper-based metal lines.

Abstract translation: 通过在填充有含铜金属的沟槽（104）的三个侧壁（1055）处设置加强层（105），可以补偿低k材料（102）的减少的热机械约束至少 从而降低电子迁移效应，从而降低具有金属化层（包括低k电介质材料（102））与铜基金属线组合的复杂半导体器件的使用寿命。

公开(公告)号：WO2010097190A1

公开(公告)日：2010-09-02

申请号：PCT/EP2010/001091

申请日：2010-02-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  AUBEL, Oliver ,  HOHAGE, Joerg ,  FEUSTEL, Frank ,  PREUSSE, Axel ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： AUBEL, Oliver ,  HOHAGE, Joerg ,  FEUSTEL, Frank ,  PREUSSE, Axel

IPC: H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76864 ,  Y10S438/906

Abstract: During the formation of complex metallization systems a conductive cap layer (122C) may be formed on a copper-containing metal region (122A) in order to enhance the electromigration behaviour without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed so as to provide for superior surface conditions of the sensitive dielectric material (121) and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.

Abstract translation: 在形成复杂的金属化系统期间，可以在含铜金属区域（122A）上形成导电覆盖层（122C），以增强电迁移行为，而不会不利地影响整个导电性。 同时，可以进行热化学处理，以便提供敏感电介质材料（121）的优异表面条件并且还抑制碳消耗，这常常导致敏感的ULK材料的材料特性的显着变化 。

公开(公告)号：WO2010022973A1

公开(公告)日：2010-03-04

申请号：PCT/EP2009/006262

申请日：2009-08-28

Applicant: ADVANCED MICRO DEVICES INC. ,  SEIDEL, Robert ,  FEUSTEL, Frank ,  RICHTER, Ralf

Inventor： SEIDEL, Robert ,  FEUSTEL, Frank ,  RICHTER, Ralf

IPC: H01L23/48 ,  H01L23/532

CPC classification number: H01L23/53276 ,  H01L23/481 ,  H01L2221/1094 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: In a semiconductor device a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.

Abstract translation: 在半导体器件中，可以基于含碳材料形成延伸穿过器件的衬底的通孔通孔，从而与高温工艺相提供优异的兼容性，同时与掺杂的半导体材料相比，还提供优异的电性能 喜欢。 因此，在一些说明性实施例中，通孔过孔可以在用于形成关键电路元件的任何工艺步骤之前形成，从而基本上避免了通孔通孔结构与对应的半导体器件的器件级别的任何干扰。 因此，可以实现高效率的三维集成方案。

公开(公告)号：WO2010022969A1

公开(公告)日：2010-03-04

申请号：PCT/EP2009/006257

申请日：2009-08-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  WERNER, Thomas ,  FROHBERG, Kai ,  FEUSTEL, Frank

Inventor： WERNER, Thomas ,  FROHBERG, Kai ,  FEUSTEL, Frank

IPC: H01L21/321 ,  H01L21/768

CPC classification number: H01L21/7684 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76832

Abstract: During the manufacturing of advanced metallization systems, a dielectric cap layer formed on a sensitive dielectric material may be partially maintained during a CMP process for removing excess metal, thereby avoiding the necessity for depositing a dedicated etch stop material, as may be required in conventional approaches when substantially completely consuming the dielectric cap material during the CMP process. Hence, reduced process complexity and/or enhanced flexibility may be accomplished in combination with increased integrity of the low-k dielectric material.

Abstract translation: 在高级金属化系统的制造过程中，在CMP工艺中可以部分地保持形成在敏感电介质材料上的电介质盖层，以去除多余的金属，从而避免沉积专用蚀刻停止材料的必要性，如常规方法中所需要的 当在CMP工艺期间基本上完全消耗电介质盖材料时。 因此，降低的工艺复杂性和/或增强的柔性可以与低k介电材料的增加的完整性相结合来实现。