公开(公告)号：EP1737284A2

公开(公告)日：2006-12-27

申请号：EP06012739.6

申请日：2006-06-21

Applicant: CANON KABUSHIKI KAISHA

Inventor： Furukawa, Masao Canon K.K. ,  Tsuruoka, Yuji Canon K.K. ,  Mori, Takashi Canon K.K. ,  Yamaguchi, Nobuhito Canon K.K. ,  Kamiya, Seiichi Canon K.K.

IPC: H05K3/12

CPC classification number: H05K3/125 ,  H05K3/245 ,  H05K3/4664 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/1476 ,  Y10S428/901

Abstract: A circuit pattern forming method is provided which can reduce a possibility of undesired short-circuits being produced in the circuit by satellites formed when fabricating a conductive pattern and thereby can form a highly reliable printed circuit board. To that end, this invention overlappingly draws a conductive pattern (11) and an insulating pattern (13) of a predetermined thickness by scanning a liquid ejection head and a substrate (10) relative to each other a plurality of times while ejecting droplets of a conductive pattern forming solution (11) and an insulating pattern forming solution (13). When forming the conductive pattern and the insulating pattern that adjoin each other on the substrate, the step of forming the insulating pattern of at least one scan is executed between the conductive pattern forming steps that are executed the plurality of times until the conductive pattern has a predetermined thickness.

Abstract translation: 提供一种电路图案形成方法，其可以减少在制造导电图案时形成的卫星在电路中产生不期望的短路的可能性，从而可以形成高度可靠的印刷电路板。 为此，本发明通过多次扫描液体喷射头和基板（10），同时喷射液滴的液滴而重叠地绘制具有预定厚度的导电图案（11）和绝缘图案（13） 导电图案形成溶液（11）和绝缘图案形成溶液（13）。 当在衬底上形成彼此相邻的导电图案和绝缘图案时，在多次执行的导电图案形成步骤之间执行形成至少一次扫描的绝缘图案的步骤，直到导电图案具有 预定厚度。

公开(公告)号：EP1341231A3

公开(公告)日：2006-07-19

申请号：EP03250539.8

申请日：2003-01-29

Applicant: STMicroelectronics, Inc.

Inventor： Chiu, Anthony M. ,  Siegel, Harry Michael

IPC: H01L21/48

CPC classification number: H01L21/481 ,  H01L21/4857 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/09781 ,  H05K2201/09881 ,  H05K2203/0278 ,  H01L2924/00014

Abstract: A system and method is disclosed for providing mechanical planarization of a sequential build up substrate for an integrated circuit package. A planarization plate is placed in contact with an uneven external surface of a dielectric layer that covers underlying functional circuit elements and filler circuit elements. A heating element in the planarization plate flattens protruding portions of the external surface of the dielectric layer to create a flat external surface on the dielectric layer. After the flat external surface of the dielectric layer has cooled, it is then covered with a metal conductor layer. The method of the present invention increases the number of sequential buildup layers that may be placed on a sequential buildup substrate.

Abstract translation: 一种系统和方法被游离缺失盘在集成电路封装，用于提供连续的积聚基板的机械平坦化。 平坦化板被放置在接触上的介电层的不平坦的外表面做了下面的功能的电路元件和电路元件填料盖。 在平坦化板的加热元件变平突出的介电层的外部表面的部分，以在介电层上创建一个平坦的外表面。 该介电层的平坦外表面已经冷却之后，将其然后覆盖有金属导体层。 本发明的方法中增加顺序堆积层的数量也可以在连续的堆积基板进行放置。

公开(公告)号：EP1677582A2

公开(公告)日：2006-07-05

申请号：EP05027867.0

申请日：1996-12-19

Applicant: IBIDEN CO., LTD.

Inventor： Mori, Yoji Ibiden Co., Ltd. ,  Kawamura, Yoichiro Ibiden Co., Ltd.

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

Abstract: A printed wiring board in which an opening existing around a pad which is a photovia land is arranged so that it is not overlapped with the pad, the area of an opening existing around a pad and that of another opening are equalized, the quantity of resin which is filled in each opening or is equalized throughout a printed wiring board and the quantity of resin overflowing from each opening or when resin is filled in each opening or is uniformed is provided. According to such a printed wiring board, a reliable printed wiring board wherein secure connection is enabled without causing disconnection can be realized when a circuit pattern provided on an interlayer insulating board formed on the printed wiring board and a conductor pad are connected by arranging an opening existing around a conductor pad so that it is not overlapped with the conductor pad and substantially equalizing the quantity of resin which is filled in an opening around a conductor pad and that of resin which is filled in another opening.

Abstract translation: 印刷电路板，其中存在于作为光电二极管的焊盘周围的开口布置成使其不与焊盘重叠，存在于焊盘周围的开口的面积和另一个开口的面积相等，树脂的量 填充在每个开口中或在整个印刷线路板上均匀化，并且设置从每个开口溢出的树脂量或当树脂在每个开口中填充或均匀时。 根据这样的印刷电路板，当通过布置开口来连接设置在形成在印刷线路板上的层间绝缘板上的电路图案和导体焊盘时，可以实现其中安全连接不会导致断开的可靠的印刷线路板 存在于导体焊盘周围，使得其不与导体焊盘重叠，并且基本上均匀地填充在导体焊盘周围的开口中的树脂的量和填充在另一个开口中的树脂的量。

公开(公告)号：EP1425949B1

公开(公告)日：2006-03-08

申请号：EP02732644.6

申请日：2002-04-22

Applicant: Thomson Licensing

Inventor： HIRT, Hermann ,  HEINI, Hubert ,  WAGNER, Paul-Heinz

IPC: H05K3/28

CPC classification number: H05K3/28 ,  H05K1/0263 ,  H05K2201/0195 ,  H05K2201/09881

Abstract: The object is to provide a printed circuit board which is also suitable for relatively high currents and is more resistant to environmental influences such as moisture and mechanical loads. The thickness of the conductor tracks (2) is made appreciably greater than 100 µm, and the intermediate spaces between the conductor tracks (2) are filled with a filling material (3) which has greatest possible adhesion to the conductor tracks (2), to the base plate (1) and to the solder resist mask (4) applied to the arrangement, being filled in such a way that the printed circuit board has a substantially planar surface without interruptions or depressions.

Abstract translation: 本发明的目的是提供一种印刷电路板，该印刷电路板也适用于较高的电流并且更耐环境影响，例如湿度和机械负载。 导体带（2）的厚度明显大于100μm，并且导体带（2）之间的中间空间填充有与导体带（2）具有最大可能粘附性的填充材料（3） （1）以及应用于该装置的阻焊掩模（4），以这样的方式填充，使得印刷电路板具有基本平坦的表面而没有中断或凹陷。

公开(公告)号：EP1631134A1

公开(公告)日：2006-03-01

申请号：EP05253770.1

申请日：2005-06-17

Applicant: San -Ei Kagaku Kabushiki Kaisha

Inventor： Sato, Kiyoshi c/o San-Ei Kaguku Kabushiki Kaisha ,  Kitamura, Kazunori c/o San-Ei Kaguku Kabushiki K.

IPC: H05K3/46

CPC classification number: H05K3/4614 ,  H05K3/205 ,  H05K3/328 ,  H05K3/423 ,  H05K2201/09881 ,  H05K2201/10378

Abstract: A multilayer circuit board comprises a conductor wiring layer (5,6), and an insulation layer (7), wherein the conductor wiring layer (5,6) and the insulation layer (7) are laminated alternately, wherein the conductor wiring layer (5,6) is electrically connected by a via (4) through the insulation layer (7), wherein the via (4) is filled with a conductor material (3), and wherein the conductor material (3) is junctured to the conductor wiring layer (5,6) with an alloy (1,2).

Abstract translation: 多层电路板包括导体布线层（5,6）和绝缘层（7），其中导体布线层（5,6）和绝缘层（7）交替层叠，其中导体布线层 5,6）通过通孔（4）通过绝缘层（7）电连接，其中通孔（4）填充有导体材料（3），并且其中导体材料（3）被接合到导体 布线层（5,6）与合金（1,2）。

公开(公告)号：EP1314172B1

公开(公告)日：2005-04-20

申请号：EP01960431.3

申请日：2001-06-30

Applicant: Moeller GmbH ,  Schmitz, Gerd

Inventor： SCHMITZ, Gerd

IPC: H01C17/065

CPC classification number: H05K1/167 ,  H01C17/0652 ,  H05K1/0257 ,  H05K1/095 ,  H05K3/386 ,  H05K2201/0323 ,  H05K2201/09881 ,  H05K2203/1453 ,  Y10T29/49099

Abstract: The invention relates to an electronic assembly, in particular, for low power consumption electric switching devices such as low power contactors, time relays or the like. In order to provide protection against input current pulses, an ohmic resistor (6) is provided in the form of a resistive layer that is applied by pressing.

Abstract translation: 电子组件技术领域本发明涉及一种电子组件，特别是用于诸如低功率接触器，时间继电器等的低功耗电子开关设备。 为了提供针对输入电流脉冲的保护，以通过按压施加的电阻层的形式提供欧姆电阻器（6）。

公开(公告)号：EP1085352A3

公开(公告)日：2003-01-08

申请号：EP00307892.0

申请日：2000-09-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiraoka, Toshiro c/o Kabushiki Kaisha Toshiba ,  Asakawa, Koji c/o Kabushiki Kaisha Toshiba ,  Hotta, Yasuyuki c/o Kabushiki Kaisha Toshiba

IPC: G02B6/12 ,  H01L23/498 ,  H05K3/46

CPC classification number: H05K3/4614 ,  B82Y20/00 ,  G02B6/1225 ,  G03F7/0002 ,  H01L2924/0002 ,  H01P1/2005 ,  H05K1/0306 ,  H05K1/0313 ,  H05K3/107 ,  H05K3/185 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/46 ,  H05K2201/0116 ,  H05K2201/0376 ,  H05K2201/09881 ,  H05K2201/10378 ,  Y10T29/49126 ,  H01L2924/00

Abstract: Disclosed is a three dimensional structure comprising a porous body (1) and a plurality of regions (2) having a substance loaded in the porous body. In one embodiment the average period of a part of the plural regions loaded with the substance is 0.1 to 2µm to form a structure having a photonic band gap. In another embodiment the substance loaded in the porous body is a conductive material, thus forming a three dimensional wiring pattern.

公开(公告)号：EP1053507A4

公开(公告)日：2002-07-24

申请号：EP99939643

申请日：1999-06-29

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON

IPC: G03F7/00 ,  H01C17/06 ,  H01C17/07 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/06 ,  H05K3/38 ,  G03C5/00

CPC classification number: H05K1/167 ,  G03F7/00 ,  H01C17/07 ,  H05K3/0023 ,  H05K3/025 ,  H05K3/048 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/1461

Abstract: A method for manufacturing a microelectronic assembly to have a resistor (12) on a circuit board (10). The method entails applying a photosensitive dielectric to a substrate (18) to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion (22). An electrically resistive film (14) is then applied to the dielectric layer and the dielectric layer is developed so that a portion of the resistive film remains over the second portion to form the resistor. A second dielectric layer (32) is then applied, photoimaged and developed to form openings (34). Terminations (16) can then be formed in the openings by known plating techniques. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or other nickel alloy and a sacrificial backing such as a layer of copper.

Abstract translation: 一种用于制造微电子组件的方法有一个电阻器，并且特别是金属电阻片，具有期望的加工和尺寸特性。 该方法基因反弹需要施加光敏介电到基材以形成介电层。 该介电层被成像的照片，以在基片上的第一区域中聚合所述介电层的第一部分，留下所述电介质层的未聚合的剩余部分。 然后电阻性电影被施加到介电层和所述介电层被显影以它们的同时除去未聚合部分和的部分中的电阻膜，覆盖在该未聚合部分，如图在第二部分做了电阻膜-遗体的一部分 以形成电阻器。 另一种方法是为了应用电阻膜-前介电层暴露于辐射，然后通过电阻电影暴露介电层。 所述电阻优选膜是多层膜，没有包括电阻层，颜色：诸如NiP的，镍铬或另一种含镍基合金，和牺牲背衬：如铜层。

公开(公告)号：EP1168901A2

公开(公告)日：2002-01-02

申请号：EP01112310.6

申请日：2001-05-19

Applicant: rotra Leiterplatten Produktions- und Vetriebs-GmbH

Inventor： Opitz, Rudi Walter ,  Stuckmann, Walter Paul Fritz

IPC: H05K3/46 ,  H01F17/00

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H05K1/165 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0143 ,  H05K2203/0759

Abstract: Mehrlagen-Leiterplatten-Verbundkörper (5) mit mindestens zwei flächig übereinander angeordneten Leiterplatten (9), welche jeweils aufweisen eine elektrisch isolierende Trägerplatte (10), elektrisch leitende Leiterbahnen (11), die auf mindestens einer Seite der Trägerplatte (10) vorgesehen sind und Ausnehmungen (12), die seitlich von den Leiterbahnen (11) und zur Trägerplatte (10) hin durch die Trägerplatte (10) begrenzt werden, und mit mindestens einer zwischen den Leiterplatten (9) angeordneten Verbundfolie (14) zum Verbinden der Leiterplatten (9), wobei die zwischen den Trägerplatten (10) der jeweiligen Leiterplatten (9) angeordneten Ausnehmungen (12) im wesentlichen vollständig mit einer Kunstharz-Masse (13) ausgefüllt sind und wobei die mindestens zwei Leiterplatten (9) und die mindestens eine Verbundfolie (14) miteinander verpreßt sind.

Abstract translation: 多层电路板复合体包括具有在电两个电路板（9）绝缘支撑板（10）在所述板的一侧上，导电通路（11），和凹口（12），以晚反弹限途径; 和所述电路板之间设置一复合箔（14），以将它们连接。 所述凹部填充有人工树脂（13）。 电路板和复合箔被压在一起。 因此独立claimsoft包括用于生产多层电路板的方法。 优选的特征：所述导电通路具有的厚度为400微米米。 该凹陷都填充到99.9％以上。 人造树脂是从气泡基本上不含。 该复合箔是用人造树脂浸渍的玻璃纤维材料。

公开(公告)号：EP1114439A2

公开(公告)日：2001-07-11

申请号：EP99937726.0

申请日：1999-07-30

Applicant: Kulicke & Soffa Holdings, Inc.

Inventor： STRANDBERG, Jan, I. ,  CHAZAN, David, J. ,  SKINNER, Michael, P.

IPC: H01L21/00

CPC classification number: H01L23/5385 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0353 ,  H05K2203/0585 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05647

Abstract: A method for forming low-impedance high density deposited-on-laminate (D/L) structures (10) having reduced stress features reducing metallization present on the laminate printed circuit board (12). In this manner, reduced is the force per unit area exerted on the dielectric material (30) disposed adjacent to the laminate material (16) which is typically present during thermal cycling of the structure.