公开(公告)号：EP2020835B1

公开(公告)日：2012-07-25

申请号：EP08009013.7

申请日：2008-05-15

Applicant: Unimicron Technology Corp.

Inventor： Hsu, Shih-Ping

IPC: H05K3/34 ,  H05K3/24

CPC classification number: H05K3/3473 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/05671 ,  H01L2224/13109 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2203/043 ,  H05K2203/0542 ,  H01L2924/00014

公开(公告)号：EP1119048B1

公开(公告)日：2011-11-09

申请号：EP99944820.2

申请日：1999-09-24

Applicant: TOYO KOHAN Co., Ltd

Inventor： SAIJO, Kinji, c/o Toyo Kohan Co., Ltd. ,  YOSHIDA, Kazuo, c/o Toyo Kohan Co., Ltd. ,  OHSAWA, Sinji, c/o Toyo Kohan Co., Ltd.

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L21/4842 ,  B23K20/04 ,  B23K20/233 ,  B23K2201/34 ,  B23K2203/10 ,  B23K2203/12 ,  B23K2203/18 ,  B23K2203/26 ,  H01L23/49582 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H05K3/062 ,  H05K3/202 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0384 ,  Y10T29/49204 ,  Y10T428/12438 ,  Y10T428/1275 ,  Y10T428/1291 ,  H01L2224/48

Abstract: A clad plate for lead frames, capable of being manufactured at a low cost and having excellent characteristics; a lead frame using the same; and a method of manufacturing the lead frame, the clad plate for lead frames being manufactured by pressure-welding a copper foil material and a nickel foil material to each other at a draft of 0.1-3 %, or by pressure-welding a copper foil material plated at one or both surfaces thereof with nickel and other copper foil material to each other at a draft of 0.1-3 %, or by pressure-welding an aluminum foil material and a nickel foil material to each other at a draft of 0.1-3 %, or by pressure-welding a copper foil material plated at one surface thereof with nickel and an aluminum foil material other than the aluminum foil material mentioned above to each other at a draft of 0.1-3 %, the clad plate having a structure of three layers of copper, nickel and copper, or copper, nickel and aluminum.

公开(公告)号：EP1786250B1

公开(公告)日：2011-10-19

申请号：EP06255825.9

申请日：2006-11-14

Applicant: TDK Corporation

Inventor： Kobuke, Hisashi c/o TDK Corporation ,  Miyakoshi, Toshinobu c/o TDK Corporation ,  Uematsu, Hiroyuki c/o TDK Corporation

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K3/281 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0269 ,  H05K1/0306 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09881 ,  H05K2203/1189 ,  H05K2203/308 ,  H01L2924/00

公开(公告)号：EP2290590A3

公开(公告)日：2011-07-27

申请号：EP10008397.1

申请日：2010-08-12

Applicant: Giesecke & Devrient GmbH

Inventor： Olbrich, Magnus

IPC: G06K19/077 ,  H01L23/52

CPC classification number: G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  H01L23/13 ,  H01L23/49855 ,  H01L2924/0002 ,  H05K1/183 ,  H05K3/305 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/0969 ,  H05K2201/10727 ,  H01L2924/00

Abstract: Ein portabler Datenträger (10) umfasst einen Datenträgerkörper (12) mit einer elektrischen Komponente (30) sowie ein elektronisches Modul (20), welches zumindest teilweise in den Datenträgerkörper (12) eingebettet ist und über eine Modulkontakteinrichtung (26) des Moduls (20) mittels eines elastischen, elektrisch leitfähigen Materials (50) unter Druckbeaufschlagung elektrisch leitend mit einer Komponentenkontakteinrichtung (32) der elektrischen Komponente (30) des Datenträgers (10) verbunden ist. Die Modulkontakteinrichtung (32) ist dabei räumlich strukturiert ausgebildet und in das elastische, elektrisch leitfähige Material (50) ist durch die räumlich strukturierte Modulkontakteinrichtung (32) eine entsprechende räumliche Struktur eingeprägt.

公开(公告)号：EP2015404A3

公开(公告)日：2010-07-21

申请号：EP08012609.7

申请日：2008-07-11

Applicant: YAMAHA CORPORATION

Inventor： Hattori, Atsuo

IPC: H01R13/11 ,  H05K3/32 ,  H01R13/20 ,  H05K3/36

CPC classification number: H05K3/365 ,  H01L2924/0002 ,  H01R12/52 ,  H01R12/718 ,  H01R13/11 ,  H01R13/20 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/209 ,  Y10T29/49204 ,  H01L2924/00

Abstract: An electronic component (1) includes a substrate (10), an interconnection element (102), and a connector (100). The interconnection element has conductivity. The interconnection element is present over the substrate. The connector is present on the interconnection element. The connector may further include, but is not limited to, a base (101), at least one stopper (17), and at least one sloped guiding surface. The base projects from the interconnection element in a first direction that is vertical to the surface of the substrate. At least one stopper projects from the base in a second direction that is parallel to the surface of the substrate. The one stopper has a stopper surface (103).

公开(公告)号：EP2186132A2

公开(公告)日：2010-05-19

申请号：EP08795418.6

申请日：2008-08-15

Applicant: Tessera, Inc.

Inventor： KWON, Jinsu c/o Tessera Inc. ,  ENDO, Kimitaka c/o Tessera Inc. ,  MORAN, Sean c/o Tessera Inc.

IPC: H01L23/48

CPC classification number: H05K1/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2203/0384 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2924/00

Abstract: An interconnection element is provided for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon. The interconnection element includes a dielectric element having a major surface. A plated metal layer including a plurality of exposed metal posts can project outwardly beyond the major surface of the dielectric element. Some of the metal posts can be electrically insulated from each other by the dielectric element. The interconnection element typically includes a plurality of terminals in conductive communication with the metal posts. The terminals can be connected through the dielectric element to the metal posts. The posts may be defined by plating a metal onto exposed co-planar surfaces of a mandrel and interior surfaces of openings in a mandrel, after which the mandrel can be removed.

公开(公告)号：EP1753278A4

公开(公告)日：2010-05-19

申请号：EP05745811

申请日：2005-05-26

Applicant: IBIDEN CO LTD ,  JSR CORP

Inventor： KARIYA TAKASHI ,  FURUTANI TOSHIKI ,  GOTO HIROFUMI ,  IWANAGA SHIN-ICHIRO

IPC: H05K3/46 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K3/28 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674

Abstract: A multilayer printed wiring board is equipped with a core board 20, a build-up layer 30 formed on the core board 20 so as to have a conductor pattern 32 on the upper surface thereof, a low-elasticity layer 40 formed on the build-up layer 30, lands 52 that are provided on the upper surface of the low-elasticity layer 40 and connected to an IC chip 70 via solder bumps 66, and conductor posts 50 that penetrate through the low-elasticity layer 40 and electrically connect the lands 52 to the conductor pattern 32. The low-elasticity layer 40 is formed of resin composition containing epoxy resin, phenol resin, cross-linked rubber particles and a hardening catalyst.

Abstract translation: 多层印刷线路板具备：芯板20;形成在芯板20上从而在其上表面上具有导体图案32的积层30;形成在积层30上的低弹性层40; 上层30，设置在低弹性层40的上表面上并通过焊料凸点66连接到IC芯片70的焊盘52以及贯穿低弹性层40并且电连接焊盘的导体柱50 52连接到导体图案32.低弹性层40由包含环氧树脂，酚醛树脂，交联橡胶颗粒和硬化催化剂的树脂组合物形成。

公开(公告)号：EP1677585A4

公开(公告)日：2010-05-19

申请号：EP05704388

申请日：2005-01-28

Applicant: IBIDEN CO LTD

Inventor： KARIYA TAKASHI ,  FURUTANI TOSHIKI

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/24 ,  H05K3/28 ,  H05K3/40

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/111 ,  H05K1/115 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/09881 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a core substrate 20; a build-up layer 30 formed on the core substrate 20 and having a conductor pattern 32 on an upper surface; a low elastic modulus layer 40 formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a semiconductor chip 70; and conductor posts 50 that are passing through the low elastic modulus layer 40 and electrically connecting lands 52 with conductor patterns 32. The conductor posts 50 are formed to have the diameters of an upper portion and a lower portion of 80µm, the diameter of an intermediate portion of 35µm, the height of 200µm, and the aspect ratio Rasp (height/minimum diameter) of 5.7 and the maximum diameter/minimum diameter of 2.3.

Abstract translation: 多层印刷线路板10包括：核心基板20; 形成在核心基板20上且在上表面上具有导体图案32的堆积层30; 形成在积层30上的低弹性模量层40; 设置在低弹性模量层40的上表面上并通过焊料凸点66连接到半导体芯片70的焊盘52; 以及导体柱50，该导体柱50穿过低弹性模量层40并且将平台52与导体图案32电连接。导体柱50被形成为具有80μm的上部和下部的直径，中间体的直径 部分为35μm，高度为200μm，长宽比Rasp（高度/最小直径）为5.7，最大直径/最小直径为2.3。

公开(公告)号：EP2180770A1

公开(公告)日：2010-04-28

申请号：EP08167159.6

申请日：2008-10-21

Applicant: ATOTECH Deutschland GmbH

Inventor： Lamprecht, Sven ,  Matejat, Kai-Jens ,  Ewert, Ingo

IPC: H05K3/34 ,  H01L21/60

CPC classification number: H05K3/3473 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05657 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K3/06 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2924/00

Abstract: Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one contact area, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface, iv) electroplate a solder deposit layer containing a tin or tin alloy onto the conductive layer and v) etch away an amount of the solder deposit layer containing tin or tin alloy sufficient to remove the solder deposit layer from the solder mask layer area leaving a solder material layer on the at least one contact area.

Abstract translation: 描述了在衬底上形成焊料沉积物的方法，其包括以下步骤：i）提供包括表面承载电路的衬底，其包括至少一个接触区域，ii）形成放置在衬底表面上的焊料掩模层，以及 图案化以暴露所述至少一个接触区域，iii）使包括焊料掩模层和至少一个接触区域的整个衬底区域与适于在衬底表面上提供导电层的溶液接触，iv）电镀焊料沉积层 在导电层上含有锡或锡合金，以及v）蚀刻一定量的包含锡或锡合金的焊料沉积层，其足以从焊料掩模层区域移除焊料沉积层，从而在至少一个 接触面积

公开(公告)号：EP1503216B1

公开(公告)日：2010-04-14

申请号：EP03758872.0

申请日：2003-10-24

Applicant: JSR Corporation

Inventor： Sato, Katsumi JSR Corporation ,  Inoue, Kazuo JSR Corporation

IPC: G01R1/073 ,  H01R11/01 ,  H01L21/66

CPC classification number: G01R1/07314 ,  G01R1/06711 ,  G01R1/06733 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R11/01 ,  H01R12/523 ,  H05K1/116 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2203/0733 ,  H01L2924/00