公开(公告)号：EP1018146A4

公开(公告)日：2007-10-17

申请号：EP99925964

申请日：1999-05-27

Applicant: DET INT HOLDING LTD

Inventor： JITARU IONEL

IPC: H01F27/06 ,  H05K1/02 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K7/20 ,  H01L21/00

CPC classification number: H05K1/0204 ,  H01F27/06 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/021 ,  H05K1/141 ,  H05K1/165 ,  H05K1/182 ,  H05K3/0061 ,  H05K7/209 ,  H05K2201/066 ,  H05K2201/086 ,  H05K2201/09054 ,  H05K2201/09063 ,  H05K2201/09072 ,  H05K2201/09572 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/10166 ,  H05K2201/10416 ,  H05K2201/10666 ,  H01L2924/00

Abstract: A transformer group in which a multitude of transformers (110A and 110B) are used to supply energy to a single load. The transformers (110A and 110B) are connected in series; in order to assist in providing a "flux equalizing" effect, the invention includes a flux equalizer circuit (112A and 112B). The flux equalizer circuit (112A and 112B) provides a series of flux windings. Each flux winding is associated with a single transformer. The windings are arranged in parallel. In this manner, a balancing of the output of the transformers is obtained; the power output from each transformer is "sensed" by its associated flux winding which is "shared" with the other transformers via their own associated flux winding. Power is processed then through the secondary windings, rectifiers, and output filters to a common load.

公开(公告)号：EP1631133A1

公开(公告)日：2006-03-01

申请号：EP05018904.2

申请日：2005-08-31

Applicant: Synergy Microwave Corporation

Inventor： Rohde, Meta ,  Rebel, Reimund ,  Poddar, Ajay Kumar ,  Schoepf, Klaus Juergen

IPC: H05K1/11

CPC classification number: H05K3/3442 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/244 ,  H05K3/368 ,  H05K2201/09481 ,  H05K2201/10666 ,  Y02P70/613 ,  Y10T29/49165

Abstract: A printed circuit board having one or more vias disposed in the surface area of a pad. The pad may serve as a connection point between the printed circuit board and another circuit board and is disposed along the edge of the board such that the vias do not form half vias.

Abstract translation: 一种具有设置在垫的表面区域中的一个或多个通孔的印刷电路板。 垫可以用作印刷电路板和另一电路板之间的连接点，并且沿着板的边缘布置，使得通孔不形成半通孔。

公开(公告)号：EP1484950A2

公开(公告)日：2004-12-08

申请号：EP04008025.1

申请日：2004-04-01

Applicant: Novar GmbH

Inventor： Gernhardt, Angelika ,  Goulet, Thomas ,  Menzel, Carsten ,  Ollik, Waldemar

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/403 ,  H05K1/0284 ,  H05K3/0052 ,  H05K3/3405 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/42 ,  H05K2201/09118 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/10666 ,  H05K2203/0455 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49789

Abstract: Ein Verfahren zur Kontaktierung der Leiterbahnen einer Schaltungsplatine (1) mit den Leiterbahnen eines Bauteiles (10) in MID-Technologie umfasst folgende Schritte:

Auf dem Nutzen, aus dem die Schaltungsplatine gewonnen wird, werden die Leiterbahnen mindestens bis zum Rand der Schaltungsplatine geführt.
Längs dieses Randes wird der Nutzen im Bereich der Leiterbahnen mit Durchgangsbohrungen (6d) versehen.
Die Durchgangsbohrungen werden galvanisch durchkontaktiert.
Die aus dem Nutzen herausgetrennte Schaltungsplatine wird relativ zu dem MID-Bauteil so positioniert, dass die aneinander grenzenden Leiterbahnen von Schaltungsplatine und MID-Bauteil miteinander verlötbar sind.

Zweckmäßig erhält die Schaltungsplatine deckungsgleich zu den an ihrem Rand endenden Leiterbahnen rückseitig elektrische Kontaktierungsflächen (6b), welche über metallisierte und durchkontaktierte Bohrungen mit den vorderseitigen Leiterbahnen (5) elektrisch verbunden sind.

Abstract translation: 该方法包括以前者中的布局制造电路板（1）的导电轨道（5），其中轨道延伸超过限定稍后面向MID部件（10）的边缘的分隔线，提供通过 至少在轨道区域沿着分离线的孔（6d），电穿孔接触（6e）孔，将电路板与前者分开，并将每个电路板定位成相对于MID部件接触，并将相邻的轨道焊在一起 。 还包括以下独立权利要求：（a）制造多于一个电路板的方法。

公开(公告)号：EP1235233A3

公开(公告)日：2004-01-14

申请号：EP02076768.7

申请日：1994-09-13

Applicant: Tyco Electronics Corporation

Inventor： Fang, Shou-Mean ,  Siden, Denis ,  Thompson, Mark ,  Zhang, Michael

IPC: H01C1/14 ,  H01C7/02 ,  H01C17/28

CPC classification number: H01C17/28 ,  H01C1/1406 ,  H01C7/027 ,  H01C17/06586 ,  H05K1/182 ,  H05K3/0097 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/10469 ,  H05K2201/10666

Abstract: Laminar electrical devices, in particular circuit protection devices, contain two laminar electrodes, with a PTC element between them, and a cross-conductor which passes through the thickness of the device and contacts one only of the two electrodes. This permits connection to both electrodes from the same side of the device. It also makes it possible to carry out the steps for preparing such devices on an assembly which corresponds to a number of individual devices, with division of the assembly as the final step.

公开(公告)号：EP1342294A1

公开(公告)日：2003-09-10

申请号：EP01964214.9

申请日：2001-08-20

Applicant: DI/DT, Inc. ,  Roy, Apurba

Inventor： ROY, Apurba

IPC: H01R13/46

CPC classification number: H01R12/57 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/52 ,  H05K3/3426 ,  H05K3/368 ,  H05K2201/1031 ,  H05K2201/10666 ,  H05K2201/10856 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49211 ,  H01L2924/00

Abstract: A low impedance surface mount connector (20) having an I-shaped cross section for connecting between the first and second circuit boards (51, 61).

公开(公告)号：EP1145608A1

公开(公告)日：2001-10-17

申请号：EP99961680.8

申请日：1999-11-19

Applicant: AlliedSignal Inc.

Inventor： POMMER, Richard, J.

IPC: H05K3/36 ,  H05K3/46 ,  H05K1/14

CPC classification number: H05K3/462 ,  H01L2224/83138 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/09701 ,  H05K1/141 ,  H05K3/305 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4069 ,  H05K3/4623 ,  H05K3/4647 ,  H05K2201/0195 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2201/10977 ,  H05K2201/2036 ,  H05K2203/063 ,  H05K2203/1189 ,  Y10T428/24562 ,  H01L2924/00

Abstract: A printed circuit assembly (100) and method of making the same facilitates the attachment of high density modules (120) onto a printed circuit board (110). In one embodiment, the high density modules are attached to the printed circuit board using an adhesive having a conductive material disposed within at least one via. A printed circuit assembly and method of making the same utilize in another embodiment an interlayer interconnecting technology incoporating conductive posts that are deposited on one of a pair of contact pads formed on a module that opposes a printed circuit board and is thereafter bonded to the other in the pair of contact pads during lamination. Fusible material may be utilized in the conductive posts to facilitate mechanical bonding to a contact pad, and the posts project through a dielectric layer disposed between the printed circuit boards, thereby forming the electrical connections between the boards at discrete locations. The conductive posts may also comprise a conductive ink.

公开(公告)号：EP0405828B1

公开(公告)日：1998-09-23

申请号：EP90306739.5

申请日：1990-06-20

Applicant: AT&T Corp.

Inventor： Clark, William Albert ,  Oien, Michael Ackman ,  Pelosi, Walter

IPC: H05K3/34

CPC classification number: H05K3/3484 ,  H05K1/0269 ,  H05K3/281 ,  H05K3/3452 ,  H05K3/363 ,  H05K2201/10666 ,  H05K2203/0113 ,  H05K2203/0195 ,  H05K2203/0338 ,  H05K2203/043

公开(公告)号：EP0834921A2

公开(公告)日：1998-04-08

申请号：EP97203302.1

申请日：1992-12-30

Applicant: TESSERA, INC.

Inventor： Distefano, Thomas H. ,  Khandros, Igor ,  Grube, Gary W. ,  Ehrenberg, Scott G.

IPC: H01L23/538

CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/0298 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H01L2924/00

Abstract: The invention relates to a method of making a multi-layer circuit assembly. Said method comprises the steps of providing a first circuit panel (544) having a dielectric body with oppositely directed top and bottom surfaces, contacts (538) on its top surface at locations of a first pattern, terminals (530) on its bottom surface, and through-conductors (527) electrically connected to said terminals and extending to the top surface of the panel, and a second circuit panel (562) having a dielectric body with a bottom surface and terminals (530) at locations of said first pattern on the bottom surface of such panel, said providing step including the step of customizing said first circuit panel by selectively treating the top surface of such panel so that less than all of the through conductors of such panel are connected to contacts of such panel; stacking said circuit panels in superposed, top-surface to bottom surface relation so that the top surface of said first circuit panel faces the bottom surface of said second circuit panel at a first interface and said first patterns on said facing surfaces are in registration with one another, with said contacts of said first panel being aligned with said terminals of said second panel at least some locations of said inregistration patterns; and non-selectively connecting all of said aligned contacts and terminals at said interface, whereby less than all of said through conductors of said customized panel are connected to terminals of said adjacent panel. The invention also relates to a multi-layer circuit assembly.

Abstract translation: 本发明涉及一种制造多层电路组件的方法。 所述方法包括以下步骤：提供具有电介质体的第一电路面板（544），所述电介质体具有相反指向的顶部和底部表面，其顶表面上的第一图案位置处的触点（538），其底表面上的端子（530） 和电连接到所述端子并延伸到所述面板的顶表面的贯穿导体（527），以及第二电路板（562），所述第二电路板（562）具有电介质体，所述电介质体具有底表面和在所述第一图案的位置处的端子 所述提供步骤包括定制所述第一电路板的步骤，所述步骤通过选择性地处理所述板的顶部表面以使得所述板的所有贯通导体都少于所述板的触点连接; 将所述电路面板叠置成叠置的顶面到底面关系，使得所述第一电路面板的顶面在第一界面处面向所述第二电路面板的底面，并且在所述面对的表面上的所述第一图案与一个 另一方面，所述第一面板的所述触点与所述第二面板的所述端子对准所述对齐图案的至少一些位置; 并且在所述接口处非选择性地连接所有所述对齐的触点和端子，由此所述定制面板的少于所有的所述贯通导体连接到所述相邻面板的端子。 本发明还涉及一种多层电路组件。

公开(公告)号：EP0795906A2

公开(公告)日：1997-09-17

申请号：EP97104269.2

申请日：1997-03-13

Applicant: NEC CORPORATION

Inventor： Inoue, Tatsuo

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15312 ,  H05K1/0269 ,  H05K1/144 ,  H05K3/3463 ,  H05K3/363 ,  H05K3/4614 ,  H05K2201/041 ,  H05K2201/094 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10666 ,  H05K2201/10681

Abstract: An electronic-circuit assembly of the present invention comprises a plurality of film carriers which are stacked. Respective film carriers have a plurality of through-holes. One of through-holes is provided on corresponding position to another through-hole in the stacked direction of the substrate. Two of adjacent film carriers are connected by the corresponding through-holes. A connection member is provided in two of adjacent through-holes in the stacked direction of the substrates. A connection state between film carriers can be easily checked. Since it is visually checked that solder appears inside the topmost through-hole. Furthermore, wiring lengths for connection between substrates can be reduced. Since the plurality of substrates are three-dimensionally connected.

Abstract translation: 本发明的电子电路组件包括堆叠的多个薄膜载体。 各胶片载体具有多个通孔。 在基板的堆叠方向上的另一通孔的相应位置上设置有一个通孔。 两个相邻的胶片载体通过相应的通孔连接。 连接构件沿着基板的堆叠方向设置在两个相邻的通孔中。 可以容易地检查胶片载体之间的连接状态。 由于目视检查焊料是否出现在最上方通孔内。 此外，可以减少基板之间的连接的布线长度。 由于多个基板是三维连接的。

公开(公告)号：EP0529577B1

公开(公告)日：1996-10-09

申请号：EP92114444.0

申请日：1992-08-25

Applicant: Hughes Aircraft Company

Inventor： Feigenbaum, Haim ,  Crumly, William R. ,  Schreiber, Christopher M.

IPC: G01R1/073 ,  H05K3/20 ,  H05K3/40

CPC classification number: G01R1/073 ,  H05K3/205 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10666 ,  H05K2203/0113 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/167