公开(公告)号：EP2141972A4

公开(公告)日：2011-01-05

申请号：EP08740252

申请日：2008-04-11

Applicant: MURATA MANUFACTURING CO

Inventor： YUDA KAZUYUKI ,  IEKI TSUTOMU

IPC: H05K3/46

CPC classification number: H05K1/141 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/19105 ,  H05K1/0218 ,  H05K1/183 ,  H05K1/187 ,  H05K3/007 ,  H05K3/20 ,  H05K3/284 ,  H05K3/303 ,  H05K3/46 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0715 ,  H05K2201/0979 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/167 ,  Y10T29/4913 ,  H01L2224/0401

Abstract: [Problem] To provide a reliable component-embedded module that allows a reduction in cost and an increase in yield. [Solving Means] A component-embedded module A includes a module substrate 1 having wiring electrodes 2 on the upper surface thereof, first circuit components 7 mounted on the wiring electrodes 2, a sub-module 10 disposed on an area on which no wiring electrodes 2 are formed, and an insulating resin layer 20 formed on the entire upper surface of the module substrate in such a manner that the insulating resin layer 20 covers at least parts of the first circuit components and sub-module. The second circuit components 15 including an integrated circuit element are mounted on the sub-module 10 or embedded therein. Via conductors 3 are formed through the module substrate 1 from the lower surface thereof and are directly coupled to terminal electrodes 14 on the lower surface of the sub-module 10. By using a substrate having a wiring accuracy higher than that of the module substrate 1, a reliable component-embedded module is obtained.

公开(公告)号：EP2184957A1

公开(公告)日：2010-05-12

申请号：EP09252576.5

申请日：2009-11-09

Applicant: Nitto Denko Corporation

Inventor： Ishii, Jun ,  Naitou, Toshiki ,  Honjo, Mitsuru

IPC: H05K1/02 ,  H05K3/46 ,  G11B5/48

CPC classification number: H05K3/4685 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/06 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: An end of a first line and an end of a second line of a first write wiring pattern are arranged on both sides of a third line of a second write wiring pattern. Circular connection portions are provided at the ends of the first line and the second line. In addition, through holes are formed in respective portions of a base insulating layer below the connection portions. Each connection portion comes in contact with a connecting region of a suspension body within the through hole.

Abstract translation: 第一写入布线图案的第一行的末端和第二行的末端布置在第二写入布线图案的第三行的两侧。 在第一行和第二行的末端提供圆形连接部分。 另外，在连接部分下方的基底绝缘层的各个部分中形成通孔。 每个连接部分与通孔内的悬挂体的连接区域接触。

公开(公告)号：EP2001274A3

公开(公告)日：2009-11-11

申请号：EP08157592.0

申请日：2008-06-04

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Yamano, Takaharu, Shinko Electric Industries Co., Ltd.

IPC: H05K3/40

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K3/205 ,  H05K3/4038 ,  H05K3/423 ,  H05K3/4605 ,  H05K3/4647 ,  H05K2201/0979 ,  H05K2203/0376 ,  H05K2203/063 ,  H05K2203/0733 ,  H01L2924/00

Abstract: A manufacturing method of a substrate with through electrodes 14, comprising a substrate 11 having through holes 18, and through electrodes 14 received in the through holes 18, includes a through electrode formation step of forming the through electrodes 14 on a support plate, a substrate formation step of forming the substrate 11, a through electrode reception step of stacking the substrate 11 on the support plate and receiving the through electrodes 14 in the through holes 18, a resin filling step of filling gaps between side surfaces of the through electrodes and inner walls of the through holes of the substrate 11 with a resin 12, and a support plate removal step of removing the support plate after the resin filling step.

公开(公告)号：EP1645023A4

公开(公告)日：2009-07-01

申请号：EP04776671

申请日：2004-06-17

Applicant: MOTOROLA INC

Inventor： SPARLING LARRY A ,  REPPLINGER SCOTT W ,  WINEINGER EUGENE L

IPC: H02M1/00 ,  H01L25/00 ,  H05K20060101 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H02M7/003 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0263 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10151 ,  H05K2201/10166 ,  Y02P70/611 ,  H01L2924/00

Abstract: A printed circuit board having a first switching device (S1 or S2), a second switching device (S3 or S4), a third switching device (S5 or S6), and a common source node (26 or 166) that are each mounted to a surface of the printed circuit board (50 or 150). The printed circuit board further includes at least a first set of conductive paths in a first layer, a second set of conductive paths in a second layer, and a plurality of vias that connects the first layer to the second layer. The first set of conductive paths provides electrical conductivity between the common source node, the first switching device, the second switching device, and third switching device. The second set of conductive paths in the second layer provides electrical conductivity between the common source node, the first switching device, and the third switching device. The physical distance between the first low side switching device and the common source node and the distance between the third low side switching device and the common source node is greater than a distance between the second low side switching device and the common source node.

公开(公告)号：EP2011376A1

公开(公告)日：2009-01-07

申请号：EP07742003.2

申请日：2007-04-13

Applicant: Panasonic Corporation

Inventor： KAWANO, Hiroshi c/o Panasonic Corporation ,  FUJIMURA, Munenori c/o Panasonic Corporation ,  NARUSE, Takumi c/o Panasonic Corporation ,  YAMAGUCHI, Shuichiro c/o Panasonic Corporation ,  HASHIMOTO, Yoshinori c/o Panasonic Corporation

IPC: H05K1/02

CPC classification number: H05K1/0243 ,  H01L2224/82047 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H04B3/54 ,  H04B3/56 ,  H04B2203/5483 ,  H04L27/2626 ,  H04L27/2647 ,  H05K1/112 ,  H05K1/186 ,  H05K3/4614 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10689 ,  H05K2203/061

Abstract: A circuit module is mounted with an IC that modulates and demodulates a multicarrier signal. The circuit module has a laminated board, which is provided internally with a plurality of conductive layers laminated having insulating layers in between, and an IC, which is provided with a plurality of ground terminals to be grounded. Of the plurality of conductive layers, a conductive layer provided proximate to the IC configures a ground layer electrically connected to the plurality of ground terminals.

公开(公告)号：EP1981317A3

公开(公告)日：2008-10-29

申请号：EP08011580.1

申请日：1996-12-19

Applicant: IBIDEN CO., LTD.

Inventor： Mori, Yoji ,  Kawamura, Yoichiro

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881

Abstract: A multilayered printed wiring board in which an interlayer insulating layer (134) is formed on a base material (131) on which a lower conductor circuit (132A) is formed, an upper conductor circuit (137) is formed on the interlayer insulating layer and the lower and upper conductor circuits are electrically connected via plural via holes (136) which are collectively formed. Preferably, said via holes share their land and the form of said land is any of the shape of a tear, an ellipse and a circle.

Abstract translation: 一种多层印刷电路板，其中在形成有下导体电路（132A）的基底材料（131）上形成有层间绝缘层（134），在所述层间绝缘层上形成上导体电路（137） 下导体电路和上导体电路通过共同形成的多个通孔（136）电连接。 优选地，所述通孔共享它们的陆地，并且所述平台的形式是泪液，椭圆形和圆形的任何形状。

公开(公告)号：EP1111969B1

公开(公告)日：2008-02-06

申请号：EP00126690.7

申请日：2000-12-05

Applicant: International Business Machines Corporation

Inventor： Frech, Roland, Dr. ,  Klink, Erich ,  Rehm, Simone ,  Virag, Helmut ,  Winkel, Thomas-Michael, Dr. ,  Chamberlin, Bruce ,  Becker, Wiren Dale ,  Ma, Wai Mon

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/0979 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

公开(公告)号：EP1060645B1

公开(公告)日：2007-05-30

申请号：EP99910902.8

申请日：1999-03-05

Applicant: Obducat AB

Inventor： WIKSTRÖM, Bo ,  OLSSON, Lennart

IPC: H05K1/02

CPC classification number: H05K1/0242 ,  H01L23/367 ,  H01L23/5283 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0209 ,  H05K1/0265 ,  H05K1/111 ,  H05K2201/0373 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An electronics device comprising a carrier, such as a printed circuit board, a substrate or a chip, and an electric conductor on a surface of the carrier. The surface of the conductor (2) facing away from the carrier has a surface structure (3, 4; 6, 7) in the form of flanges which are defined by etched grooves.

公开(公告)号：EP1645023A2

公开(公告)日：2006-04-12

申请号：EP04776671.2

申请日：2004-06-17

Applicant: MOTOROLA, INC.

Inventor： SPARLING, Larry, A. ,  REPPLINGER, Scott, W. ,  WINEINGER, Eugene, L.

IPC: H02M1/00

CPC classification number: H02M7/003 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0263 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10151 ,  H05K2201/10166 ,  Y02P70/611 ,  H01L2924/00

Abstract: A printed circuit board having a first switching device (S1 or S2), a second switching device (S3 or S4), a third switching device (S5 or S6), and a common source node (26 or 166) that are each mounted to a surface of the printed circuit board (50 or 150). The printed circuit board further includes at least a first set of conductive paths in a first layer, a second set of conductive paths in a second layer, and a plurality of vias that connects the first layer to the second layer. The first set of conductive paths provides electrical conductivity between the common source node, the first switching device, the second switching device, and third switching device. The second set of conductive paths in the second layer provides electrical conductivity between the common source node, the first switching device, and the third switching device. The physical distance between the first low side switching device and the common source node and the distance between the third low side switching device and the common source node is greater than a distance between the second low side switching device and the common source node.

公开(公告)号：EP0817548B1

公开(公告)日：2006-04-05

申请号：EP96942586.7

申请日：1996-12-19

Applicant: IBIDEN CO., LTD.

Inventor： MORI, Yoji ,  KAWAMURA, Yoichiro

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

Abstract: A printed wiring board (1) such that openings (8L) formed around a pad (12L) which is a photo-via land do not overlap a pad (12L) and the area of each of the openings (8L) around the pad (12L) is equal to that of each of the other openings (8), the amount of resin (13) with which each of the openings (8, 8L) is filled is equal to that with which each of the openings (8L) is filled over the whole wiring board (1), and the amounts of resin (13) overflowing from the openings (8, 8L) are equal to each other. The circuit pattern provided on the upper surface of an interlayer insulating layer formed on the printed wiring board can be connected to a conductor pad area without causing any defective connection, providing a highly-reliable printed wiring board.