公开(公告)号：EP2360998A1

公开(公告)日：2011-08-24

申请号：EP11165890.2

申请日：2008-03-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shen, Xiaolan ,  Ye, Qingsong ,  Wei, Konggang

IPC: H05K1/02

CPC classification number: H05K1/0218 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/0298 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/09627

Abstract: A printed circuit board and a design method thereof are disclosed. The design method includes: wiring signal lines on an area basis at inner layers adjacent to outer surface layers; arranging the outer surface layers with no wiring or few wirings and interconnecting the outer surface layers through through vias, so that the outer surface layers function as a primary ground; and setting parameters of a line width and a layer height to control a target impedance value. The printed circuit board includes outer surface layers and two inner layers therebetween. The inner layers adjacent to the outer surface layers are used for arranging signal lines on an area basis; and the outer surface layers are arranged with no wiring or few wirings and are interconnected as a primary ground through through vias. The invention also discloses a mainboard of a terminal product using the printed circuit board.

Abstract translation: 公开了印刷电路板及其设计方法。 该设计方法包括：在与外表面层相邻的内层处基于区域布线信号线; 将外表面层布置成没有布线或几条布线，并且通过通孔将外表面层互连，使得外表面层用作主地面; 并设置线宽和层高的参数以控制目标阻抗值。 印刷电路板包括外表面层和它们之间的两个内层。 与外表面层相邻的内层用于在区域的基础上布置信号线; 并且外表面层布置成没有布线或几个布线，并且通过通孔作为主地相互连接。 本发明还公开了使用印刷电路板的终端产品的主板。

公开(公告)号：EP1936682A4

公开(公告)日：2011-08-03

申请号：EP06811835

申请日：2006-10-16

Applicant: IBIDEN CO LTD

Inventor： KARIYA TAKASHI ,  TANAKA HIRONORI

IPC: H01L23/12 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09827 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/05599

公开(公告)号：EP2346310A2

公开(公告)日：2011-07-20

申请号：EP11161217.2

申请日：2002-09-26

Applicant: FUJITSU LIMITED

Inventor： Kusagaya, Toshihiro ,  Yoneda, Yasuhiro ,  Mizutani, Daisuke ,  Iijima, Kazuhiko ,  Suwa, Yuji

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/4641 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/01087 ,  H05K1/0216 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1394

Abstract: An organic multilayer wiring circuit board comprises: a signal layer (L4); a first insulating layer (24) made of resin and arranged on the signal layer (L4); a lamination body arranged on the first insulating layer (24), which lamination body includes: an electric power source layer (L3); a ground layer (L2); and a second insulating layer (16) made of polyimide and provided between the electric power source layer (L3) and the ground layer (L2); the second insulating layer (16) having a thickness of 4 to 25µm and a thermoplastic adhesive property on both faces thereof; a third insulating layer (14) made of resin and arranged on the lamination body; and an uppermost conductive layer (L1) arranged on the third insulating layer (14), on which an electronic component is to be mounted.

Abstract translation: 有机多层布线电路板包括：信号层（L4）; 由树脂制成并布置在信号层（L4）上的第一绝缘层（24）; 设置在所述第一绝缘层（24）上的层压体，所述层压体包括：电源层（L3）; 地层（L2）; 以及设置在所述电源层（L3）和所述接地层（L2）之间的由聚酰亚胺制成的第二绝缘层（16）; 所述第二绝缘层（16）具有4至25μm的厚度并且在其两个面上具有热塑性粘合性质; 由树脂制成并布置在层压体上的第三绝缘层（14） 和布置在第三绝缘层（14）上的最上面的导电层（L1），电子部件将安装在该最上面的导电层（L1）上。

公开(公告)号：EP2170028A4

公开(公告)日：2011-07-20

申请号：EP07790573

申请日：2007-07-10

Applicant: IBIDEN CO LTD

Inventor： TAKAHASHI MICHIMASA

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096

公开(公告)号：EP1705973B1

公开(公告)日：2011-05-11

申请号：EP06014607.3

申请日：1996-10-23

Applicant: IBIDEN CO., LTD.

Inventor： Kawamura, Yoichiro ,  Murase, Hideki ,  Asai, Motoo

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

公开(公告)号：EP2070159B1

公开(公告)日：2010-12-22

申请号：EP07813572.0

申请日：2007-07-31

Applicant: Raytheon Company

Inventor： PUZELLA, Angelo M. ,  CROWDER, Joseph M. ,  DUPUIS, Patricia S. ,  FALLICA, Michael C. ,  FRANCIS, John B. ,  LICCIARDELLO, Joseph A.

IPC: H01Q21/00

CPC classification number: H01Q21/0087 ,  H03H7/38 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/09145 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09718 ,  H05K2201/09727 ,  H05K2201/209 ,  H05K2203/061 ,  Y10T29/49165

Abstract: A tile subarray includes an upper multi-layer assembly (UMLA) provided from a first plurality of printed circuit boards and a lower multi-layer assembly (LMLA) provided from a second plurality of printed circuit boards. Each of the UMLA and LMLA includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the UMLA and LMLA. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the UMLA and LMLA.

公开(公告)号：EP1286578B1

公开(公告)日：2010-12-22

申请号：EP02026472.7

申请日：1998-10-12

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo, Ibiden Co., Ldt ,  Shimada, Kenichi, Ibiden Co., Ldt ,  Noda, Kouta, Ibiden Co., Ldt ,  Kayriya, Takashi, Ibiden Co., Ldt ,  Segawa, Hiroshi, Ibiden Co., Ldt

IPC: H05K3/46

CPC classification number: B32B3/00 ,  H05K3/0094 ,  H05K3/383 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10S428/901 ,  Y10T428/24917

公开(公告)号：EP2001271A3

公开(公告)日：2010-11-03

申请号：EP08251545.3

申请日：2008-04-28

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Davis, Thomas J. ,  Lauffer, John M. ,  Desai, Subahu D. ,  McNamara, James J. Jnr. ,  Markovich, Voya R.

IPC: H05K1/00 ,  H05K3/46 ,  H05K3/44 ,  H05K3/40

CPC classification number: H05K3/429 ,  H05K3/0032 ,  H05K3/0038 ,  H05K3/427 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0143 ,  H05K2203/0554 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of making a multilayered circuitized substrate (101) in which a continuous process is used to form electrically conductive layers (65) which each will form part of a sub-composite (75, 75', 75"). The sub-composites (75, 75', 75") are then aligned such that openings (57) within the conductive layers (65) are also aligned, the sub-composites (75, 75', 75") are then bonded together, and a plurality of holes (113) are then laser drilled through the entire thickness of the bonded structure. The dielectric layers (67, 69) used in the sub-composites (75, 75', 75") do not include continuous or semi-continuous fibers therein, thus expediting hole formation there-through.

公开(公告)号：EP1903842B1

公开(公告)日：2010-08-25

申请号：EP08000185.2

申请日：1999-06-23

Applicant: Ibiden Co., Ltd.

Inventor： Nishiwaki, Yoko ,  Noda, Kouta

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4626 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/0094 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4602 ,  H05K2201/0108 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0278 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1157 ,  Y10T29/49155

公开(公告)号：EP2150096A1

公开(公告)日：2010-02-03

申请号：EP07743324.1

申请日：2007-05-14

Applicant: Ibiden Co., Ltd.

Inventor： TAKAHASHI, Michimasa ,  AOYAMA, Masakazu

IPC: H05K3/46

CPC classification number: H05K3/4691 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0366 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/1536 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A wiring board of the present invention is structured with first substrate 1, second substrate 2 having a smaller mounting area than that of first substrate 1, and base substrate 3 laminated between first substrate 1 and second substrate 2, and having vias 44 formed in at least either first substrate 1 or second substrate 2 and a through-hole 63 which penetrates base substrate 3.

Abstract translation: 本发明的布线基板由第1基板1，安装面积小于第1基板1的第2基板2，以及层叠在第1基板1和第2基板2之间的基板3构成， 第一基板1或第二基板2中的至少一个以及贯通基底基板3的贯通孔63。