摘要:
Plural via portions formed on a package substrate of a BGA include a first through-hole portion extended in the plane direction by an extension wiring connected to a land portion and a second through-hole portion that is arranged on the land portion serving as pad-on-via, whereby high-density wiring and multi-function of the BGA can be realized by using the package substrate having a two-layer wiring structure. Accordingly, cost for the package substrate can be reduced, and hence, cost for the BGA can be reduced, compared to a multi-layer wiring structure having four or six wiring layers.
摘要:
PROBLEM TO BE SOLVED: To provide a semiconductor device improved in robustness against impacts to a bonding pad when probing and bonding. SOLUTION: The semiconductor device with a bonding pad 130 on a semiconductor substrate 10 includes an upper Cu layer 100 formed on a lower surface of the bonding pad 130 via a barrier metal and having a larger Cu area ratio than a layer on which circuit wiring is formed, and a lower Cu layer 200 electrically insulated from the upper Cu layer 100 and formed on the side of the semiconductor substrate 10 from the upper Cu layer 100. COPYRIGHT: (C)2009,JPO&INPIT
摘要:
PROBLEM TO BE SOLVED: To provide a technology capable of reducing a semiconductor device in size (plane size) regarding a technology applied to the semiconductor device, especially, a semiconductor device having bonding pads. SOLUTION: In the semiconductor device; an input/output circuit 11 is formed on a semiconductor substrate 30, a ground wiring 7 and power supply line 8 pass over it, furthermore, and a conductor layer 51 used for bonding pad 4 is formed on it. Further, the input/output circuit 11 is formed by MISFET elements of nMISFET forming region 21 and pMISFET forming region 27, resistive elements of resistive element forming regions 22, 26 functioning as a protection element, and diode elements of diode element forming regions 23, 25. An interconnection 53, connected to these protection elements, of lower layer than the ground wiring 7 and the power supply line 8 is connected to a conductor layer 51, in such a way that it is drawn out at a location between the nMISFET forming region 21 and the pMISFET forming region 27, and at a drawing region 24 between the ground wiring 7 and the power supply line 8. COPYRIGHT: (C)2007,JPO&INPIT
摘要:
PROBLEM TO BE SOLVED: To provide a semiconductor package which can reduce top-metal spreading resistance of a control pad of a power device such as a MOSFET.SOLUTION: The semiconductor package comprises a semiconductor device having a first major surface including a first electrode and a second major surface including a second electrode 126 and a control electrode 120, where the control electrode is disposed in a corner of the second major surface, and the first electrode, the second electrode, and the control electrode are electrically connected to a surface of a planar support 128 without a bonding wire.
摘要:
PROBLEM TO BE SOLVED: To reduce manufacturing cost for a semiconductor-integrated circuit device having a flip-chip structure by reducing a chip size. SOLUTION: The semiconductor-integrated circuit device includes a semiconductor chip 100 having a plurality of input/output cells 105, a plurality of pads 101, 102 formed on a surface of the semiconductor chip, and inter-pad wiring 103, 104 formed on the surface of the semiconductor chip 100, and electrically connecting some of the plurality of input/output cells 105 and some of the plurality of pads 101, 102. The plurality of pads 101, 102 are arranged in a square lattice shape at the center of the semiconductor chip 100, and also arranged zigzag at least at one of four corners of the semiconductor chip 100. COPYRIGHT: (C)2011,JPO&INPIT
摘要:
PROBLEM TO BE SOLVED: To provide a structure by which a cost of a package substrate of a semiconductor device can be reduced in compared with a case wherein a multilayer wiring board of four layers or six layers, etc. is used. SOLUTION: A plurality of vias provided to the package substrate 3 of a BGA 7 comprise: first through holes 3e lead out in a plane direction by leading wirings 3h connecting to lands 3d; and second through holes 3g acting as pad-on vias arranged on the lands 3d. Thereby high-densification of wirings and high function of BGA 7 are enabled by using the package substrate 3 of a two-layer wiring structure. COPYRIGHT: (C)2007,JPO&INPIT