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    Inactivity triggered self clocking logic family
    3.
    发明授权
    Inactivity triggered self clocking logic family 有权
    不活动触发自我计时逻辑家族

    公开(公告)号：US08575964B2

    公开(公告)日：2013-11-05

    申请号：US13426776

    申请日：2012-03-22

    Applicant: Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    Inventor： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

    IPC: H03K19/00

    CPC classification number: H03K19/0966 ,  H03K19/0013

    Abstract: Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

    Abstract translation: 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

    SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT
    5.
    发明申请
    SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT 有权
    用于冗余和改进的半导体芯片堆叠

    公开(公告)号：US20120326333A1

    公开(公告)日：2012-12-27

    申请号：US13607680

    申请日：2012-09-08

    Applicant: Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    Inventor： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

    IPC: H01L25/00

    CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

    Abstract translation: 包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。 第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成 提供第一芯片组件的完全功能实例的功能的功能块。 层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。 多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。

    Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices
    6.
    发明授权
    Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
    用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管

    公开(公告)号：US08263472B2

    公开(公告)日：2012-09-11

    申请号：US13324486

    申请日：2011-12-13

    Applicant: John E. Barth, Jr. ,  Kerry Bernstein

    Inventor： John E. Barth, Jr. ,  Kerry Bernstein

    IPC: H01L21/76

    CPC classification number: H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L23/535 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.

    Abstract translation: 半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层， 第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽 设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

    Soft error correction in sleeping processors
    7.
    发明授权
    Soft error correction in sleeping processors 有权
    睡眠处理器中的软错误校正

    公开(公告)号：US08234554B2

    公开(公告)日：2012-07-31

    申请号：US12170462

    申请日：2008-07-10

    Applicant: Kerry Bernstein ,  Norman J. Rohrer

    Inventor： Kerry Bernstein ,  Norman J. Rohrer

    IPC: H03M13/00

    CPC classification number: H03M13/15 ,  G06F11/1008 ,  H03M13/098 ,  H03M13/13 ,  H03M13/1505 ,  H03M13/19

    Abstract: An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.

    Abstract translation: 在处理器进入睡眠模式之前，将物理逻辑寄存器和锁存内容逐行生成在处理器内的处理器内，生成错误校正码，并检查后来生成的校验码位 处理器唤醒时出现软错误，例如作为上电顺序的一部分。

    METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE
    8.
    发明申请
    METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE 有权
    基于可制造性，测试覆盖和可选择的诊断覆盖的组合设计集成电路的方法

    公开(公告)号：US20120066657A1

    公开(公告)日：2012-03-15

    申请号：US12880228

    申请日：2010-09-13

    Applicant: Kerry Bernstein ,  James A. Culp ,  Leah M.P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

    Inventor： Kerry Bernstein ,  James A. Culp ,  Leah M.P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.

    Abstract translation: 披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。 根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。 或者，可以根据DFM修改建立集成电路的测试覆盖。 或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。 或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。 在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

    Vertical through-silicon via for a semiconductor structure
    9.
    发明授权
    Vertical through-silicon via for a semiconductor structure 有权
    用于半导体结构的垂直通硅硅通孔

    公开(公告)号：US08097525B2

    公开(公告)日：2012-01-17

    申请号：US12201580

    申请日：2008-08-29

    Applicant: John E. Barth, Jr. ,  Kerry Bernstein

    Inventor： John E. Barth, Jr. ,  Kerry Bernstein

    IPC: H01L21/00

    CPC classification number: H01L23/481 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.

    Abstract translation: 半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。 穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

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