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公开(公告)号:US20170083042A1
公开(公告)日:2017-03-23
申请号:US14860670
申请日:2015-09-21
Applicant: Apple Inc.
Inventor: Shawn X. ARNOLD , G. Kyle LOBISSER , Mark BEESLEY
IPC: G06F1/16
CPC classification number: G06F1/16 , G06F1/1658
Abstract: This application relates to systems, methods, and apparatuses for reducing bending stresses and tension from damaging components of a computing device. A component of the computing device can be connected to a spacer that can distribute impact forces and resist bending when an impact force is applied to the computing device. Additionally, a bracket can be connected to a circuit board of the computing device to further help distribute impact forces and resist bending. The bracket can be ring shaped and surround components connected to the circuit board to intercept impact forces from contacting the components.
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公开(公告)号:US20140091439A1
公开(公告)日:2014-04-03
申请号:US13631769
申请日:2012-09-28
Applicant: APPLE INC.
Inventor: Shawn X. ARNOLD , Matthew E. LAST
IPC: H01L29/02 , H01L21/78 , H01L21/762
CPC classification number: H01L29/0657 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L21/822 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381
Abstract: One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate.
Abstract translation: 用于形成用于电子器件的成形衬底的一个实施例可以形成成形周边以限定衬底表面上的衬底形状。 成形的周边可以至少部分地延伸到基底中。 随后的变薄过程可以去除衬底材料并且使形状的周边有效地从衬底形成成形的模具。
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公开(公告)号:US20140084425A1
公开(公告)日:2014-03-27
申请号:US13629544
申请日:2012-09-27
Applicant: APPLE INC.
Inventor: Shawn X. ARNOLD , Matthew E. LAST
IPC: H01L23/498 , H01L21/56
CPC classification number: H01L24/19 , H01L23/3121 , H01L23/3128 , H01L23/49822 , H01L23/5389 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/12042 , H01L2924/00014 , H01L2924/00
Abstract: One embodiment of a perimeter trench sensor array package can include a thinned substrate device that includes a perimeter trench formed near the edges of the device that can be configured to be thinner than a central portion of the thinned substrate device. The perimeter trench can include bond pads that can couple to electrical elements included in the thinned substrate device. The thinned substrate device can be attached to a core layer that can in turn support one or more resin layers. The core layer and the resin layers can form a printed circuit board assembly, a flex cable assembly or a stand-alone module.
Abstract translation: 周边沟槽传感器阵列封装的一个实施例可以包括减薄的衬底器件,其包括在器件边缘附近形成的周边沟槽,该周边沟槽可以被配置为比薄的衬底器件的中心部分更薄。 周边沟槽可以包括可以耦合到包括在薄化衬底器件中的电气元件的接合焊盘。 可以将薄化的衬底装置附接到可以依次支撑一个或多个树脂层的芯层。 芯层和树脂层可以形成印刷电路板组件,柔性电缆组件或独立模块。
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公开(公告)号:US20140076621A1
公开(公告)日:2014-03-20
申请号:US13957342
申请日:2013-08-01
Applicant: Apple Inc.
Inventor: Shawn X. ARNOLD , Jeffrey M. THOMA , Connor R. DUKE , Yanchu XU , Nelson J. KOTTKE
CPC classification number: H01G4/01 , B23K26/22 , H01G2/06 , H01G2/10 , H01G4/224 , H01G4/228 , H01G4/40 , H05K1/181 , H05K3/3442 , H05K13/0465 , H05K2201/10015 , H05K2201/10636 , H05K2201/10962 , H05K2201/2045 , Y02P70/611 , Y02P70/613
Abstract: The described embodiments relate generally to printed circuit boards (PCBs) including a capacitor and more specifically to designs for mechanically isolating the capacitor from the PCB to reduce an acoustic noise produced when the capacitor imparts a piezoelectric force on the PCB. Conductive features can be mechanically and electrically coupled to electrodes located on two ends of the capacitor. The conductive features can be placed in corners where the amplitude of vibrations created by the piezoelectric forces is relatively small. The conductive features can then be soldered to a land pattern on the PCB to form a mechanical and electrical connection while reducing an amount of vibrational energy transferred from the capacitor to the PCB.
Abstract translation: 所描述的实施例通常涉及包括电容器的印刷电路板(PCB),更具体地涉及用于将电容器与PCB机械隔离的设计,以减少当电容器在PCB上施加压电力时产生的声学噪声。 导电特征可以机械地和电耦合到位于电容器两端的电极。 导电特征可以放置在由压电力产生的振动幅度相对较小的拐角处。 然后可以将导电特征焊接到PCB上的焊盘图案以形成机械和电连接,同时减少从电容器传递到PCB的振动能量的数量。
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公开(公告)号:US20250071888A1
公开(公告)日:2025-02-27
申请号:US18781453
申请日:2024-07-23
Applicant: Apple Inc.
Inventor: Shawn X. ARNOLD , Zhongqing GONG , Anping GUO
Abstract: The present disclosure describes a structure with a substrate, a damping structure, and a capacitor structure. The damping structure is disposed over the substrate and includes a rigid material layer and a damping material layer disposed on the rigid material layer. The damping material layer includes a damping material with a tensile strength of about 20 MPa, a Young's modulus of about 0.5 GPa, and an elongation of about 10%. The capacitor structure is disposed over the damping structure, in which the damping structure mitigates (or eliminates) a transfer of piezoelectric and electrostrictive vibrations generated by the capacitor structure to the substrate.
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公开(公告)号:US20170084395A1
公开(公告)日:2017-03-23
申请号:US15086813
申请日:2016-03-31
Applicant: Apple Inc.
Inventor: Paul A. MARTINEZ , Jason C. SAUERS , Shawn X. ARNOLD
CPC classification number: A62C31/22 , A62C31/02 , A62C33/04 , E06B5/16 , E06B5/162 , F16L5/04 , H01G4/012 , H01G4/1218 , H01G4/232 , H01G4/30 , H01G4/38 , H05K1/18 , H05K2201/10015
Abstract: This application relates to capacitors that resist deformation because of the configuration of their conductive and dielectric layers. The capacitors are multilayer capacitors that include multiple dielectric and conductive layers. The dielectric layers can be arranged in a way that creates a rigid barrier or dead zone, which can resist mechanical deformation when the multilayer capacitor is charged. In some embodiments, two or more multilayer capacitors are stacked together in an arrangement that causes each of the multilayer capacitors to cancel any deformations of the other when the multilayer capacitors are charged. In this way, noise exhibited by the multilayer capacitors can be reduced.
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公开(公告)号:US20140159214A1
公开(公告)日:2014-06-12
申请号:US13902727
申请日:2013-05-24
Applicant: Apple Inc.
Inventor: Shawn X. ARNOLD
IPC: H01L21/52 , H01L23/495
CPC classification number: H01L21/52 , H01L21/4803 , H01L23/24 , H01L23/5389 , H01L23/562 , H01L24/00 , H01L2924/12042 , H05K1/0271 , H05K1/185 , H05K3/0035 , H05K3/4652 , H05K2203/1469 , H01L2924/00
Abstract: A method for mounting and embedding a thinned integrated circuit within a substrate is provided. In one embodiment, the thinned integrated circuit can receive one or more biasing substrate layers on a first surface of the thinned integrated circuit. When the thinned integrated circuit is embedded within a supporting substrate, such as a printed circuit board, the biasing substrate layers can position the thinned integrated circuit toward a centerline of the printed circuit board. Positioning the thinned integrated circuit toward the centerline can increase the resistance to breakage.
Abstract translation: 提供了一种在基板内安装和嵌入薄型集成电路的方法。 在一个实施例中,减薄的集成电路可以在稀疏集成电路的第一表面上接收一个或多个偏置衬底层。 当薄化的集成电路嵌入诸如印刷电路板的支撑衬底内时,偏压衬底层可以将薄化的集成电路定位到印刷电路板的中心线。 将减薄的集成电路朝向中心线定位可以增加抗断裂性。
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公开(公告)号:US20140084454A1
公开(公告)日:2014-03-27
申请号:US13629560
申请日:2012-09-27
Applicant: APPLE INC.
Inventor: Shawn X. ARNOLD , Matthew E. LAST
IPC: H01L21/762 , H01L23/498
CPC classification number: H01L21/762 , H01L23/498 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/26 , H01L25/0655 , H01L25/0657 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/06183 , H01L2224/131 , H01L2224/13144 , H01L2224/14183 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/2929 , H01L2224/293 , H01L2224/32145 , H01L2224/32225 , H01L2224/81141 , H01L2224/83141 , H01L2225/06513 , H01L2225/06527 , H01L2225/06551 , H01L2225/06593 , H01L2924/0002 , H01L2924/10156 , H01L2924/00 , H01L2924/00014 , H01L2924/014
Abstract: A direct multiple substrate die assembly can include a first and a second substrate, wherein each substrate can include at least one interlocking edge feature. An electrical interconnection area can be formed adjacent to or within the interlocking edge feature on each substrate and can be configured to couple one or more electrical signals between the substrates. In one embodiment, the interlocking edge feature can include one or more keying features that can enable accurate alignment between the substrates. In yet another embodiment, the direct multiple substrate die assembly can be mounted out of plane with respect to a supporting substrate.
Abstract translation: 直接多基板模具组件可以包括第一和第二基板,其中每个基板可以包括至少一个互锁边缘特征。 电互连区域可以形成在每个基板上的互锁边缘特征附近或内部,并且可以被配置为在基板之间耦合一个或多个电信号。 在一个实施例中,互锁边缘特征可以包括能够实现基板之间的精确对准的一个或多个键控特征。 在另一个实施例中,直接多基板模具组件可以相对于支撑基板安装在平面外。
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公开(公告)号:US20150310991A1
公开(公告)日:2015-10-29
申请号:US14265147
申请日:2014-04-29
Applicant: Apple Inc.
Inventor: Gang NING , Shawn X. ARNOLD
Abstract: This application relates to multi-layered ceramic capacitors (MLCC) that can be surface mounted, include multiple terminals, and handle multiple voltages. The MLCC can include electrode and dielectric layers that are stacked in parallel to a printed circuit board (PCB) on which the MLCC can be attached. A set of primary conductive pads can be formed on the bottom of the MLCC in order to create a conductive interface between the PCB and the MLCC. Secondary conductive pads are formed on the side of the MLCC, and can extend perpendicular to the PCB. The secondary conductive pads are created by stacking internal electrode plates together and connecting them electrically and mechanically to each another. This arrangement provides for multiple voltages and electrical connections at the MLCC while reducing reverse piezoelectric and/or electro-striction noise.
Abstract translation: 本申请涉及可以表面安装的多层陶瓷电容器(MLCC),包括多个端子,并处理多个电压。 MLCC可以包括与可以连接MLCC的印刷电路板(PCB)平行堆叠的电极和电介质层。 可以在MLCC的底部形成一组主导电焊盘,以便在PCB和MLCC之间形成导电接口。 二次导电焊盘形成在MLCC的侧面,并可垂直于PCB延伸。 通过将内部电极板堆叠在一起并将它们彼此电连接和机械地连接而产生次级导电焊盘。 这种布置在MLCC处提供多个电压和电连接,同时减少反向压电和/或电摩擦噪声。
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公开(公告)号:US20130285263A1
公开(公告)日:2013-10-31
申请号:US13632145
申请日:2012-09-30
Applicant: APPLE INC.
Inventor: Shawn X. ARNOLD , Terry L. GILTON , Matthew LAST
IPC: H01L23/498 , H01L21/308
CPC classification number: H05K1/183 , G06F1/16 , G06F3/041 , G06K9/00053 , H01L23/24 , H01L24/11 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/81 , H01L24/85 , H01L29/0657 , H01L2224/43 , H01L2224/45015 , H01L2224/451 , H01L2224/48091 , H01L2224/48137 , H01L2224/48479 , H01L2224/85 , H01L2224/85051 , H01L2224/85186 , H01L2924/00 , H01L2924/00014 , H01L2924/10155 , H01L2924/10253 , H05K1/111 , H05K2201/09036 , H05K2201/10151 , H01L2924/20752 , H01L2224/48471 , H01L2224/4554
Abstract: A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board.
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