公开(公告)号：US5300444A

公开(公告)日：1994-04-05

申请号：US693505

申请日：1991-04-30

申请人： Atsushi Hachisuka ,  Masao Nagatomo ,  Ikuo Ogoh ,  Hideki Genjou ,  Yoshinori Okumura ,  Takayuki Matsukawa

发明人： Atsushi Hachisuka ,  Masao Nagatomo ,  Ikuo Ogoh ,  Hideki Genjou ,  Yoshinori Okumura ,  Takayuki Matsukawa

IPC分类号： H01L21/316 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/265

CPC分类号： H01L27/10844 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31612 ,  H01L27/10808

摘要： A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2. No notches occur in the polycrystalline silicon film (20) in the process of selectively removing the polycrystalline silicon film (15) and the silicon oxide film (18a) deposited thereon, employing the same mask (14), thereby not decreasing the operation speed of the field effect transistor having the gate electrode (20) formed of the polycrystalline silicon film.

摘要翻译： 包括具有堆叠电容器的存储单元的半导体存储器件具有通过选择性去除多晶硅膜（15; 20）和使用相同掩模（14）的氧化硅膜（18a; 18）而形成的堆叠结构。 连接到堆叠电容器的场效应晶体管具有由上述多晶硅膜形成的栅电极（20）。 该多晶硅膜（20）形成在半导体衬底的主表面上。 作为形成在栅电极（20）上的上层绝缘膜的上述氧化硅膜（18）的残留应力为109dyn / cm 2以下。 在使用相同的掩模（14）选择性地去除沉积在其上的多晶硅膜（15）和氧化硅膜（18a）的过程中，在多晶硅膜（20）中没有发生缺口，从而不会降低 该场效应晶体管具有由多晶硅膜形成的栅电极（20）。

公开(公告)号：US5153689A

公开(公告)日：1992-10-06

申请号：US404528

申请日：1989-09-08

申请人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

发明人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808 ,  H01L23/53257 ,  H01L2924/0002

摘要： A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

摘要翻译： 半导体存储器件的存储单元包括一个MOS晶体管（3）和一个堆叠电容器（4）。 MOS晶体管的源极/漏极区域（8a，8b）之一连接到位线（2a，2b）。 位线由MOS晶体管的源极/漏极区域到层叠电容器上方的部分的接触部分形成。 位线由具有高熔点的金属，具有高熔点的金属的硅化物或多晶硅化物形成。 由于该材料对于曝光具有低的反射率，因此提高了互连图形化的精度。

公开(公告)号：US06388295B1

公开(公告)日：2002-05-14

申请号：US09663717

申请日：2000-09-18

申请人： Tomohiro Yamashita ,  Yoshinori Okumura ,  Atsushi Hachisuka ,  Shinya Soeda

发明人： Tomohiro Yamashita ,  Yoshinori Okumura ,  Atsushi Hachisuka ,  Shinya Soeda

IPC分类号： H01L2976

CPC分类号： H01L21/823493 ,  H01L21/761 ,  H01L27/10897

摘要： The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as suppression of a leak current can be achieved even in a miniaturized structure.

摘要翻译： 半导体器件具有三重阱结构。 三井等井在深度方向具有杂质浓度分布，根据所需的功能确定。 因此，即使在小型化结构中也能够实现抑制漏电流等所需的性能。

公开(公告)号：US5173752A

公开(公告)日：1992-12-22

申请号：US690824

申请日：1991-04-26

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002 ,  Y10S257/90

摘要： A semiconductor device incloudes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅电极（4）的表面被第一绝缘膜（5）覆盖，左侧和右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

公开(公告)号：US5627093A

公开(公告)日：1997-05-06

申请号：US463809

申请日：1995-06-05

申请人： Atsushi Hachisuka ,  Yoshinori Okumura

发明人： Atsushi Hachisuka ,  Yoshinori Okumura

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/532 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  H01L29/43 ,  H01L29/49 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10873 ,  H01L29/4983 ,  H01L2924/0002

摘要： An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite lateral walls of the first conductive portion. Upper surfaces and lateral surfaces thereof are coated with insulating layers formed in separate processes. The insulating layers covering the lateral surfaces in particular are formed by a self-aligning technique requiring no mask process. Where conductive layers are formed over the wiring layer according to this invention, a film forming and patterning process for insulating the conductive portions of the wiring layer is omitted and insulation of the wiring layer is secured.

摘要翻译： 根据本发明的半导体器件的电极布线层包括由多晶硅等形成的第一导电部分和在第一导电部分的相对侧壁上形成为难熔金属硅化物层的第二导电部分。 其上表面和侧表面涂覆有分离工艺形成的绝缘层。 覆盖侧表面的绝缘层特别地由不需要掩模处理的自对准技术形成。 在根据本发明的布线层上形成导电层的情况下，省略了用于绝缘布线层的导电部分的成膜和图案化工艺，并且确保了布线层的绝缘。

公开(公告)号：US5240872A

公开(公告)日：1993-08-31

申请号：US925148

申请日：1992-08-06

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L21/8242 ,  H01L23/485 ,  H01L27/108

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002

摘要： A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅极（4）的表面被第一绝缘膜（5）覆盖，左右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

公开(公告)号：US5502324A

公开(公告)日：1996-03-26

申请号：US363548

申请日：1994-12-23

申请人： Atsushi Hachisuka ,  Yoshinori Okumura

发明人： Atsushi Hachisuka ,  Yoshinori Okumura

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/532 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  H01L29/43 ,  H01L29/49 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10873 ,  H01L29/4983 ,  H01L2924/0002

摘要： An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite lateral walls of the first conductive portion. Upper surfaces and lateral surfaces thereof are coated with insulating layers formed in separate processes. The insulating layers covering the lateral surfaces in particular are formed by a self-aligning technique requiring no mask process. Where conductive layers are formed over the wiring layer according to this invention, a film forming and patterning process for insulating the conductive portions of the wiring layer is omitted and insulation of the wiring layer is secured.

摘要翻译： 根据本发明的半导体器件的电极布线层包括由多晶硅等形成的第一导电部分和在第一导电部分的相对侧壁上形成为难熔金属硅化物层的第二导电部分。 其上表面和侧表面涂覆有分离工艺形成的绝缘层。 覆盖侧表面的绝缘层特别地由不需要掩模处理的自对准技术形成。 在根据本发明的布线层上形成导电层的情况下，省略了用于绝缘布线层的导电部分的成膜和图案化工艺，并且确保了布线层的绝缘。

公开(公告)号：US5281838A

公开(公告)日：1994-01-25

申请号：US899021

申请日：1992-06-15

申请人： Yoshinori Okumura ,  Atsushi Hachisuka

发明人： Yoshinori Okumura ,  Atsushi Hachisuka

IPC分类号： H01L23/485 ,  H01L27/108 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54

CPC分类号： H01L23/485 ,  H01L27/10805 ,  H01L2924/0002

摘要： A semiconductor device is disclosed that can form contacts with ease even if the distance between adjacent gate electrodes is reduced in accordance with larger scale integration of semiconductor devices. The semiconductor device includes a polysilicon pad 8c connected to impurity implanted layers 5a and 7a, formed over sidewalls 6a and 6b of gate electrodes 3a and 3b and insulating films 4a and 4b; and a polysilicon pad 11a connected to impurity implanted layers 5b and 7b, formed over polysilicon pad 8c with an insulating film 9 and sidewalls 10b therebetween. Even if elements are miniaturized to have reduced gate electrode length and gate electrode distance in accordance with larger scale integration of a semiconductor device, polysilicon pads 8c and 11a can be formed with ease between impurity implanted layers 5a, 7a and an upper layer wiring 13a, and between impurity implanted layers 5b, 7b and an upper layer wiring 13b, respectively. Thus, contact holes 15a and 15b can be formed without difficulty for forming upper layer wirings 13a and 13b, even if semiconductor devices are increased to larger scale integration.

摘要翻译： 公开了一种能够容易地形成接触的半导体器件，即使根据半导体器件的大规模集成，相邻栅电极之间的距离减小。 半导体器件包括连接到杂质注入层5a和7a的多晶硅焊盘8c，其形成在栅电极3a和3b的侧壁6a和6b以及绝缘膜4a和4b上; 以及与杂质注入层5b和7b连接的多晶硅焊盘11a，其形成在多晶硅焊盘8c的绝缘膜9和它们之间的侧壁10b之间。 即使元件小型化以根据半导体器件的大规模集成来减小栅极电极长度和栅极电极距离，可以容易地在杂质注入层5a，7a和上层布线13a之间形成多晶硅焊盘8c和11a， 以及杂质注入层5b，7b和上层布线13b之间。 因此，即使半导体器件增加到更大规模的集成，也可以形成上层配线13a，13b难以形成接触孔15a，15b。

公开(公告)号：US06784066B2

公开(公告)日：2004-08-31

申请号：US09960974

申请日：2001-09-25

申请人： Atsushi Hachisuka

发明人： Atsushi Hachisuka

IPC分类号： H01L2120

CPC分类号： H01L27/10894 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823468 ,  H01L27/10873 ,  H01L29/6656

摘要： A plurality of gate electrodes is formed on a semiconductor substrate having a DRAM area and a logic area. Next, sidewalls, each of which includes a silicon nitride film covering the sides of gate electrodes and a silicon oxide film covering the silicon nitride film, are formed on the sides of the gate electrodes respectively. After formation of a transistor having an LDD structure in the logic area, the silicon oxide film formed on the sides of the gate electrodes is removed by wet etching. Next, a silicon nitride film is formed on the whole surface of the semiconductor substrate, and an interlayer dielectric is formed on the silicon nitride film.

摘要翻译： 在具有DRAM区域和逻辑区域的半导体衬底上形成多个栅电极。 接下来，分别在栅电极的侧面分别形成各自包括覆盖栅电极的侧面的氮化硅膜和覆盖氮化硅膜的氧化硅膜的侧壁。 在逻辑区域中形成具有LDD结构的晶体管之后，通过湿蚀刻去除形成在栅电极侧面上的氧化硅膜。 接下来，在半导体衬底的整个表面上形成氮化硅膜，并在氮化硅膜上形成层间电介质。

公开(公告)号：US5892291A

公开(公告)日：1999-04-06

申请号：US670313

申请日：1996-06-27

申请人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

发明人： Koichiro Narimatsu ,  Shigenori Yamashita ,  Nobuyuki Yoshioka ,  Shinya Soeda ,  Atsushi Hachisuka ,  Koji Taniguchi ,  Yuki Miyamoto ,  Takayuki Saito ,  Ayumi Minamide

IPC分类号： G03F1/36 ,  G03F1/42 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H05K1/02 ,  H01L23/544

CPC分类号： G03F7/706 ,  G03F7/70633 ,  Y10T428/24802 ,  Y10T428/24917

摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.

摘要翻译： 本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件， 以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。 第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案 。 因此，可以提供考虑到像差影响的配准精度测量标记。