公开(公告)号：US20090184414A1

公开(公告)日：2009-07-23

申请号：US12347020

申请日：2008-12-31

申请人： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

发明人： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC分类号： H01L23/04 ,  H01L23/12 ,  H01L21/00 ,  H01L23/482 ,  H01L21/98

CPC分类号： H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

摘要： A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

摘要翻译： 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。

公开(公告)号：US20120049385A1

公开(公告)日：2012-03-01

申请号：US13289365

申请日：2011-11-04

申请人： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

发明人： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

摘要： A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

摘要翻译： 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。

公开(公告)号：US20090197372A1

公开(公告)日：2009-08-06

申请号：US12345858

申请日：2008-12-30

申请人： Kwon Whan HAN ,  Chang Jun PARK ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE

发明人： Kwon Whan HAN ,  Chang Jun PARK ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE

IPC分类号： H01L21/00

CPC分类号： H01L24/16 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/17 ,  H01L24/90 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/90 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014

摘要： Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.

摘要翻译： 制造晶片级堆叠封装包括对包括多个第一半导体芯片的晶片的下表面进行背面磨削的步骤。 支撑构件附接到后磨碎晶片的下表面。 一个或多个第二半导体芯片堆叠在背面研磨的晶片的相应的第一半导体芯片上。 形成第一贯通电极以电连接堆叠的第一半导体芯片和第二半导体芯片。 第三半导体芯片附着到堆叠的第二半导体芯片的最上面，第三半导体芯片具有与连接到第二贯通电极的第一贯通电极和再分配线电连接的第二贯通电极。 外部连接端子附接到第三半导体芯片的再分配线路。 第二半导体芯片和第三半导体芯片堆叠的晶片级的第一半导体芯片在芯片级被锯切以用于半导体封装。

公开(公告)号：US20080318361A1

公开(公告)日：2008-12-25

申请号：US11777388

申请日：2007-07-13

申请人： Kwon Whan HAN ,  Chang Jun PARK ,  Min Suk SUH ,  Seong Cheol KIM ,  Sung Min KIM ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM ,  Ha Na LEE

发明人： Kwon Whan HAN ,  Chang Jun PARK ,  Min Suk SUH ,  Seong Cheol KIM ,  Sung Min KIM ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM ,  Ha Na LEE

IPC分类号： H01L21/44 ,  H01L21/02

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/013

摘要： A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

摘要翻译： 一种半导体封装的制造方法，其特征在于，在设置有所述接合焊盘的半导体芯片的焊盘的外侧的部分的外表面形成有槽， 在所述槽的侧壁上形成绝缘层; 在半导体芯片上形成金属层，以填充形成有绝缘层的槽; 蚀刻金属层以同时形成用于填充槽的通过硅通孔和用于连接通过硅通孔和接合焊盘的分布层; 以及去除所述半导体芯片的后表面，使得所述贯穿硅通孔的下表面从所述半导体芯片突出。

公开(公告)号：US20090140392A1

公开(公告)日：2009-06-04

申请号：US12044420

申请日：2008-03-07

申请人： Chang Jun PARK

发明人： Chang Jun PARK

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.

摘要翻译： 提供一种半导体封装及其制造方法，用于最小化或防止由于在磨削期间使它们变薄而导致的半导体芯片体的翘曲和扭曲。 半导体封装包括半导体芯片体和基板。 半导体芯片本体具有第一表面，远离第一表面的第二表面，穿过半导体芯片主体并从第二表面突出的通孔，以及沿着栅栏的形状突出的防翘曲部 第二表面的边缘。 基板具有基板主体和连接焊盘，其形成在基板主体的上表面上，面对第​​二表面，并且与突出的贯通电极连接。

公开(公告)号：US20120009775A1

公开(公告)日：2012-01-12

申请号：US13239777

申请日：2011-09-22

申请人： Chang Jun PARK

发明人： Chang Jun PARK

IPC分类号： H01L21/28 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/05576 ,  H01L2224/06136 ,  H01L2224/11332 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/83194 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance.

摘要翻译： 半导体封装包括设置有设置在其表面上的焊盘的半导体芯片; 通孔从表面通过与第一表面相对的第二表面，并与焊盘电连接; 以及设置在第二表面处并与通孔电连接的再分配。 本发明的实施例能够显着地减小半导体封装的厚度和体积。 由于半导体封装输入和/或输出的信号的路径被缩短，所以也能进行高速运转。 它能够容易地堆叠具有晶片级的至少两个半导体封装，并且能够显着降低寄生电容。

公开(公告)号：US20100317151A1

公开(公告)日：2010-12-16

申请号：US12848472

申请日：2010-08-02

申请人： Chang Jun PARK

发明人： Chang Jun PARK

IPC分类号： H01L21/768 ,  H01L21/78

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.

摘要翻译： 提供一种半导体封装及其制造方法，用于最小化或防止由于在磨削期间使它们变薄而导致的半导体芯片体的翘曲和扭曲。 半导体封装包括半导体芯片体和基板。 半导体芯片本体具有第一表面，远离第一表面的第二表面，穿过半导体芯片主体并从第二表面突出的通孔，以及沿着栅栏的形状突出的防翘曲部 第二表面的边缘。 基板具有基板主体和连接焊盘，其形成在基板主体的上表面上，面对第​​二表面，并且与突出的贯通电极连接。

公开(公告)号：US20090039481A1

公开(公告)日：2009-02-12

申请号：US11854243

申请日：2007-09-12

申请人： Chang Jun PARK

发明人： Chang Jun PARK

IPC分类号： H01L23/495 ,  H01L21/71

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/05576 ,  H01L2224/06136 ,  H01L2224/11332 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/83194 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance.

摘要翻译： 半导体封装包括设置有设置在其表面上的焊盘的半导体芯片; 通孔从表面通过与第一表面相对的第二表面，并与焊盘电连接; 以及设置在第二表面处并与通孔电连接的再分配。 本发明的实施例能够显着地减小半导体封装的厚度和体积。 由于半导体封装输入和/或输出的信号的路径被缩短，所以也能够进行高速运转。 它能够容易地堆叠具有晶片级的至少两个半导体封装，并且能够显着降低寄生电容。

公开(公告)号：US20120175783A1

公开(公告)日：2012-07-12

申请号：US13418845

申请日：2012-03-13

申请人： Min Suk SUH ,  Chang Jun PARK

发明人： Min Suk SUH ,  Chang Jun PARK

IPC分类号： H01L23/48 ,  H01L23/46

CPC分类号： H01L23/473 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor package having an internal cooling system is presented which includes a semiconductor chip and a through-electrode. The semiconductor chip has a circuit section. The through-electrode passes through an upper surface and a lower surface the semiconductor chip. The through-electrode is electrically connected with the circuit section of the semiconductor chip. The through-electrode also has a through-hole for allowing cooling fluid to flow therethrough.

摘要翻译： 提出了一种具有内部冷却系统的半导体封装，其包括半导体芯片和通孔。 半导体芯片具有电路部分。 贯通电极通过半导体芯片的上表面和下表面。 贯通电极与半导体芯片的电路部电连接。 贯通电极还具有用于使冷却流体流过的通孔。

公开(公告)号：US20100224990A1

公开(公告)日：2010-09-09

申请号：US12639222

申请日：2009-12-16

申请人： Min Suk SUH ,  Chang Jun PARK

发明人： Min Suk SUH ,  Chang Jun PARK

IPC分类号： H01L23/34 ,  H01L25/065 ,  H01L23/538

CPC分类号： H01L23/473 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor package having an internal cooling system is presented which includes a semiconductor chip and a through-electrode. The semiconductor chip has a circuit section. The through-electrode passes through an upper surface and a lower surface the semiconductor chip. The through-electrode is electrically connected with the circuit section of the semiconductor chip. The through-electrode also has a through-hole for allowing cooling fluid to flow therethrough.

摘要翻译： 提出了一种具有内部冷却系统的半导体封装，其包括半导体芯片和通孔。 半导体芯片具有电路部分。 贯通电极通过半导体芯片的上表面和下表面。 贯通电极与半导体芯片的电路部电连接。 贯通电极还具有用于使冷却流体流过的通孔。