公开(公告)号：US20070004097A1

公开(公告)日：2007-01-04

申请号：US11171819

申请日：2005-06-30

申请人： Cheemen Yu ,  Ken Ming Wang ,  Chin-Tien Chiu ,  Chih-Chin Liao ,  Han-Shiao Chen

发明人： Cheemen Yu ,  Ken Ming Wang ,  Chin-Tien Chiu ,  Chih-Chin Liao ,  Han-Shiao Chen

IPC分类号： H01L21/82

CPC分类号： H05K1/0271 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0253 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package. The dummy circuit pattern includes a plurality of straight line segments and a plurality of interrupt patterns to breakup one or more of the straight line segments. The interrupt patterns are provided so as to not electrically isolate areas of the dummy pattern, thus providing electrical continuity across the dummy circuit pattern.

摘要翻译： 在半导体封装用基板的表面上公开了虚设电路图案。 虚拟电路图案包括多条直线段和多条中断模式，以分解一条或多条直线段。 提供中断模式，以便不电隔离虚设图案的区域，从而在虚拟电路图案上提供电连续性。

公开(公告)号：US20090263969A1

公开(公告)日：2009-10-22

申请号：US12493582

申请日：2009-06-29

申请人： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

发明人： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC分类号： H01L21/3205

CPC分类号： H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

摘要翻译： 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20070267759A1

公开(公告)日：2007-11-22

申请号：US11435518

申请日：2006-05-17

申请人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L23/48

CPC分类号： H05K3/243 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09781 ,  H05K2201/0989 ,  H01L2924/00

摘要： A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.

摘要翻译： 公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。 根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。 此外，基板可以包括包括电镀材料的虚拟电镀区域。 电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。 电镀图案的均匀分布防止成品基板中的峰和谷。

公开(公告)号：US07967184B2

公开(公告)日：2011-06-28

申请号：US11280419

申请日：2005-11-16

申请人： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

IPC分类号： B23K31/02

CPC分类号： H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

摘要翻译： 公开了一种具有低轮廓的半导体封装。 在实施例中，表面安装部件可以直接安装到半导体封装基板的芯部，使得在部件和基板芯之间不存在导电层，镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件，包括例如无源部件和各种封装半导体。

公开(公告)号：US20070269929A1

公开(公告)日：2007-11-22

申请号：US11435954

申请日：2006-05-17

申请人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L21/00 ,  H01L21/31

CPC分类号： H01L23/49838 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/09781 ,  H01L2924/00

摘要： A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.

摘要翻译： 公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。 根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。 此外，基板可以包括包括电镀材料的虚拟电镀区域。 电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。 电镀图案的均匀分布防止成品基板中的峰和谷。

公开(公告)号：US20120273968A1

公开(公告)日：2012-11-01

申请号：US13544809

申请日：2012-07-09

申请人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H05K1/11 ,  H01L23/48

CPC分类号： H05K1/111 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/0195 ,  H05K2201/0338 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

摘要： A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

摘要翻译： 公开了具有共同的电连接器和接触焊盘区域的印刷电路板。 迹线和/或通孔所在接触焊盘区域可被蚀刻掉，以确保迹线，通孔和接触焊盘之间的电气隔离。

公开(公告)号：US07592699B2

公开(公告)日：2009-09-22

申请号：US11321929

申请日：2005-12-29

申请人： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

发明人： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC分类号： H01L23/04

CPC分类号： H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

摘要翻译： 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20080054445A1

公开(公告)日：2008-03-06

申请号：US11930816

申请日：2007-10-31

申请人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Cheemen Yu ,  Hem Takiar

发明人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H01L23/562 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05015 ,  H01L2224/05023 ,  H01L2224/0605 ,  H01L2224/06151 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/15333 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

摘要翻译： 形成在半导体管芯封装中的衬底的第一侧上的刚性波形图案。 刚性波形图案与形成在基板的第二侧上的接触指状物对准并覆盖在其上。 当模制过程中衬底和裸片被封装时，刚性波形有效地减少了模具的变形和应力，从而大大减轻了模具开裂。

公开(公告)号：US20070152319A1

公开(公告)日：2007-07-05

申请号：US11321929

申请日：2005-12-29

申请人： Hem Takiar ,  Cheemen Yu ,  Ken Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

发明人： Hem Takiar ,  Cheemen Yu ,  Ken Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

摘要翻译： 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20070108257A1

公开(公告)日：2007-05-17

申请号：US11280419

申请日：2005-11-16

申请人： Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

IPC分类号： B23K31/02 ,  B23K31/00

CPC分类号： H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

摘要翻译： 公开了一种具有低轮廓的半导体封装。 在实施例中，表面安装部件可以直接安装到半导体封装基板的芯部，使得在部件和基板芯之间不存在导电层，镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件，包括例如无源部件和各种封装半导体。