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    Barrier layers
    5.
    发明授权
    Barrier layers 有权
    阻隔层

    公开(公告)号：US08508018B2

    公开(公告)日：2013-08-13

    申请号：US12890462

    申请日：2010-09-24

    申请人： Rohan N. Akolkar ,  Sridhar Balakrishnan ,  James S. Clarke ,  Christopher J. Jezewski ,  Philip Yashar

    发明人： Rohan N. Akolkar ,  Sridhar Balakrishnan ,  James S. Clarke ,  Christopher J. Jezewski ,  Philip Yashar

    IPC分类号： H01L29/00

    CPC分类号： C25D5/02 ,  C23C28/023 ,  C25D7/123 ,  H01L21/76831 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/12361 ,  Y10T428/12389 ,  H01L2924/00

    摘要： Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

    摘要翻译： 提供了制造集成电路电互连和电互连的方法。 方法包括提供具有表面的基底，所述表面具有形成在其中的特征，其中所述特征是沟槽或通孔，沉积金属层，所述金属层的金属选自由Ru，Co，Pt，Ir ，Pd，Re和Rh沉积到特征的表面上，沉积铜籽晶层，其中铜籽晶层包含掺杂剂，掺杂剂选自Mn，Mg，MgB 2。 P，B，Al，Co及其组合在金属层上，并将铜沉积到特征中。 提供了包括具有金属衬里层的铜互连的装置。 提供了具有包含钌的衬里层的器件。

    INTERLAYER INTERCONNECTS AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS
    7.
    发明申请
    INTERLAYER INTERCONNECTS AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS 审中-公开
    中间层互连及相关技术和配置

    公开(公告)号：US20140029181A1

    公开(公告)日：2014-01-30

    申请号：US13560930

    申请日：2012-07-27

    申请人： Florian Gstrein ,  Hui Jae Yoo ,  Jacob M. Faber ,  James S. Clarke

    发明人： Florian Gstrein ,  Hui Jae Yoo ,  Jacob M. Faber ,  James S. Clarke

    IPC分类号： H01L23/522 ,  G06F1/16 ,  H01L21/768

    CPC分类号： H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the present disclosure are directed towards interlayer interconnects and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, one or more device layers disposed on the semiconductor substrate, and one or more interconnect layers disposed on the one or more device layers, the one or more interconnect layers including interconnect structures configured to route electrical signals to or from the one or more device layers, the interconnect structures comprising copper (Cu) and germanium (Ge). Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例涉及层间互连和相关联的技术和配置。 在一个实施例中，一种装置包括半导体衬底，设置在半导体衬底上的一个或多个器件层，以及设置在该一个或多个器件层上的一个或多个互连层，所述一个或多个互连层包括被配置为布线 信号到或来自一个或多个器件层，包括铜（Cu）和锗（Ge）的互连结构。 可以描述和/或要求保护其他实施例。

    METHODS OF FORMING PARALLEL WIRES OF DIFFERENT METAL MATERIALS THROUGH DOUBLE PATTERNING AND FILL TECHNIQUES
    8.
    发明申请
    METHODS OF FORMING PARALLEL WIRES OF DIFFERENT METAL MATERIALS THROUGH DOUBLE PATTERNING AND FILL TECHNIQUES 有权
    通过双重图案和填充技术形成不同金属材料的平行线的方法

    公开(公告)号：US20150091174A1

    公开(公告)日：2015-04-02

    申请号：US14040191

    申请日：2013-09-27

    申请人： James S. Clarke ,  Anthony C. Schmitz ,  Richard E. Schenker

    发明人： James S. Clarke ,  Anthony C. Schmitz ,  Richard E. Schenker

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/481 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.

    摘要翻译： 一种集成电路和形成集成电路的方法，该集成电路包括包括表面的第一介电层，限定在电介质层表面中的多个第一沟槽和多个第一布线，其中，每个第一布线形成在 第一个沟渠。 集成电路还包括限定在电介质层表面中的多个第二沟槽和多个第二布线，其中每个第二布线形成在每个第二沟槽中。 此外，第一导线包括具有第一体电阻率的第一材料，并且第二导线包括具有第二体电阻率的第二材料，其中第一体电阻率和第二体电阻率不同。

    Chemically altered carbosilanes for pore sealing applications
    10.
    发明授权
    Chemically altered carbosilanes for pore sealing applications 有权
    用于孔封的化学改性碳硅烷应用

    公开(公告)号：US09269652B2

    公开(公告)日：2016-02-23

    申请号：US13995905

    申请日：2011-12-22

    申请人： David J. Michalak ,  James M. Blackwell ,  Jeffery D. Bielefeld ,  James S. Clarke

    发明人： David J. Michalak ,  James M. Blackwell ,  Jeffery D. Bielefeld ,  James S. Clarke

    IPC分类号： H01L21/76 ,  H01L23/485 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02

    CPC分类号： H01L23/485 ,  H01L21/02203 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method including forming a dielectric material including a surface porosity on a circuit substrate including a plurality of devices; chemically modifying a portion of the surface of the dielectric material with a first reactant; reacting the chemically modified portion of the surface with a molecule that, once reacted, will be thermally stable; and forming a film including the molecule. An apparatus including a circuit substrate including a plurality of devices; a plurality of interconnect lines disposed in a plurality of layers coupled to the plurality of devices; and a plurality of dielectric layers disposed between the plurality of interconnect lines, wherein at least one of the dielectric layers comprises a porous material surface relative to the plurality of devices and the surface comprises a pore obstructing material.

    摘要翻译： 一种包括在包括多个器件的电路基板上形成包括表面孔隙率的介电材料的方法; 用第一反应物化学改性电介质材料表面的一部分; 使表面的化学改性部分与一旦反应后将是热稳定的分子反应; 并形成包含该分子的膜。 一种装置，包括：包括多个装置的电路基板; 布置在耦合到所述多个装置的多个层中的多个互连线; 以及设置在所述多个互连线之间的多个电介质层，其中所述电介质层中的至少一个相对于所述多个器件包括多孔材料表面，并且所述表面包括孔阻塞材料。