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    TECHNIQUES FOR FORMING INTERCONNECTS IN POROUS DIELECTRIC MATERIALS
    4.
    发明申请
    TECHNIQUES FOR FORMING INTERCONNECTS IN POROUS DIELECTRIC MATERIALS 有权
    在多孔电介质材料中形成互连的技术

    公开(公告)号：US20150179578A1

    公开(公告)日：2015-06-25

    申请号：US14139970

    申请日：2013-12-24

    申请人： Christopher J. Jezewski ,  David J. Michalak ,  Kanwal Jit Singh ,  Alan M. Myers

    发明人： Christopher J. Jezewski ,  David J. Michalak ,  Kanwal Jit Singh ,  Alan M. Myers

    IPC分类号： H01L23/532 ,  H01L21/768

    CPC分类号： H01L23/5329 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (κ-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer. Some embodiments can be utilized, for example, in processes involving atomic layer deposition (ALD)-based and/or chemical vapor deposition (CVD)-based backend metallization of highly porous, ultra-low-κ (ULK) dielectric materials.

    摘要翻译： 公开了用于在多孔电介质材料中形成互连的技术。 根据一些实施例，可以通过用诸如氮化钛（TiN），二氧化钛（TiO 2）或其它合适的牺牲材料的牺牲孔填充材料填充其孔来临时减小主介质层的孔隙率， 与互连的金属化和介电材料相比，具有高蚀刻选择性。 在填充电介质层内形成互连之后，可以从主电介质的孔中去除牺牲孔填充材料。 在一些情况下，可以对介电常数（＆kgr--value），泄漏性能和/或时间依赖的介电击穿（TDDB）性能的最小或其他可忽略的影响进行去除和固化。 一些实施例可以用于例如涉及基于原子层沉积（ALD）的和/或化学气相沉积（CVD）的后端金属化的高度多孔，超低kgr的金属化过程。 （ULK）电介质材料。

    Self Forming Metal Fluoride Barriers for Fluorinated Low-K Dielectrics
    6.
    发明申请
    Self Forming Metal Fluoride Barriers for Fluorinated Low-K Dielectrics 审中-公开
    氟化低K电介质的自形成金属氟化物屏障

    公开(公告)号：US20100244252A1

    公开(公告)日：2010-09-30

    申请号：US12416131

    申请日：2009-03-31

    申请人： Christopher J. Jezewski ,  Daniel J. Zierath ,  Florian Gstrein

    发明人： Christopher J. Jezewski ,  Daniel J. Zierath ,  Florian Gstrein

    IPC分类号： H01L23/538 ,  H01L21/768

    CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76867 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers.

    摘要翻译： 公开了在氟化低K电介质和Cu或Cu合金互连的界面处形成氟化物金属屏障的装置和方法。 氟化物金属屏障可以防止互连与氟化低K电介质反应。 该方法可以包括在氟化低K电介质上沉积金属或金属合金薄膜。 薄膜可以包括与来自氟化低K电介质的游离氟和/或氟化合物反应以形成氟化物金属屏障的金属或金属合金元素。

    SELF FORMING METAL FLUORIDE BARRIERS FOR FLUORINATED LOW-K DIELECTRICS
    7.
    发明申请
    SELF FORMING METAL FLUORIDE BARRIERS FOR FLUORINATED LOW-K DIELECTRICS 审中-公开
    用于氟化低K电介质的自制金属氟化物阻挡层

    公开(公告)号：US20120258588A1

    公开(公告)日：2012-10-11

    申请号：US13529067

    申请日：2012-06-21

    申请人： Christopher J. Jezewski ,  Daniel J. Zierath ,  Florian Gstrein

    发明人： Christopher J. Jezewski ,  Daniel J. Zierath ,  Florian Gstrein

    IPC分类号： H01L21/768

    CPC分类号： B67D7/348 ,  G07F13/025

    摘要： A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers.

    摘要翻译： 公开了在氟化低K电介质和Cu或Cu合金互连的界面处形成氟化物金属屏障的装置和方法。 氟化物金属屏障可以防止互连与氟化低K电介质反应。 该方法可以包括在氟化低K电介质上沉积金属或金属合金薄膜。 薄膜可以包括与来自氟化低K电介质的游离氟和/或氟化合物反应以形成氟化物金属屏障的金属或金属合金元素。

    Barrier layers
    9.
    发明授权
    Barrier layers 有权
    阻隔层

    公开(公告)号：US08508018B2

    公开(公告)日：2013-08-13

    申请号：US12890462

    申请日：2010-09-24

    申请人： Rohan N. Akolkar ,  Sridhar Balakrishnan ,  James S. Clarke ,  Christopher J. Jezewski ,  Philip Yashar

    发明人： Rohan N. Akolkar ,  Sridhar Balakrishnan ,  James S. Clarke ,  Christopher J. Jezewski ,  Philip Yashar

    IPC分类号： H01L29/00

    CPC分类号： C25D5/02 ,  C23C28/023 ,  C25D7/123 ,  H01L21/76831 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T428/12361 ,  Y10T428/12389 ,  H01L2924/00

    摘要： Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

    摘要翻译： 提供了制造集成电路电互连和电互连的方法。 方法包括提供具有表面的基底，所述表面具有形成在其中的特征，其中所述特征是沟槽或通孔，沉积金属层，所述金属层的金属选自由Ru，Co，Pt，Ir ，Pd，Re和Rh沉积到特征的表面上，沉积铜籽晶层，其中铜籽晶层包含掺杂剂，掺杂剂选自Mn，Mg，MgB 2。 P，B，Al，Co及其组合在金属层上，并将铜沉积到特征中。 提供了包括具有金属衬里层的铜互连的装置。 提供了具有包含钌的衬里层的器件。