摘要:
Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.
摘要:
Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.
摘要:
Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin continuous and conformal layer, and may also limit oxidation of an underlying barrier (or other underlying surface). A dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer, and allows for dopant segregation at the interface at the top of the seed layer. Thus, electromigration performance is improved.
摘要:
Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.
摘要:
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
摘要:
One embodiment of the invention involves a refractory layer formed over a substrate during rapid thermal processing in which ambient hydrogen is used in a thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350° C. to approximately 550° C.
摘要:
A process for etching a tungsten layer formed on a semiconductor substrate is described. The etch is carried out in a parallel plate plasma reactor. The etchant gases include nitrogen trifluoride (NF.sub.3) and argon (Ar). The use of NF.sub.3 in a tungsten etching process reduces the build-up of polymers or sulfur residues on the electrode as occurs with processes utilizing sulfur or carbon fluorides as etchant gases. The process has a sufficiently high etch rate for volume production. The NF.sub.3 -Ar etch process can be used to etchback a blanket layer of deposited tungsten to form tungsten via plugs in contact areas of the device. In the via plug process, reduced micro-loading effect, that is, the tendency of some plugs to be etched away before the complete etching of the blanket layer, has been achieved. The etching of tunsten with NF.sub.3 -Ar process can be preformed in one or more steps in process utilizing several etching steps. Additionally, a tungsten etch incorporating one or more NF.sub.3 -Ar steps and one or more steps utilizing etchants such as SF.sub.6, Cl.sub.2, O.sub.2, CF.sub.4, CBrF.sub.3, CF.sub.3 Cl, CF.sub.2 Cl.sub.2 or similar etchants can be used to optimize etch rate and uniformity while obtaining the benefit of reduced residue build-up.
摘要:
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
摘要:
A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.
摘要:
The invention includes a method for controlling amplifier output power in an optical communications network. A first transmission parameter is determined at a first amplifier. In an exemplary embodiment, the first transmission parameter is a composite express signal to noise ratio. The total output power of a downstream amplifier is adjusted in response to the first transmission parameter. A system for implementing the method is also disclosed.