公开(公告)号：US10510620B1

公开(公告)日：2019-12-17

申请号：US16047043

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Steven R. Soss ,  Steven J. Bentley ,  Julien Frougier ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/092 ,  H01L27/11

Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. A first WFM for one FET is deposited over the first active nanostructure, the pillar and the second active nanostructure. The first WFM is removed from a part of the pillar. The removing creates a discontinuity in the first WFM over the first active nano structure from the first WFM over the second active nanostructure but leaves the first WFM on sidewalls of the pillar. When the first WFM surrounding the second active nanostructure is removed, the pillar and the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. Depositing a second WFM surrounding the second active nanostructure and the isolation pillar forms part of the gate for the second FET and couples the FETs together.

公开(公告)号：US20140353801A1

公开(公告)日：2014-12-04

申请号：US13906852

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Steven J. Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/761 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US20180083136A1

公开(公告)日：2018-03-22

申请号：US15268796

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Steven J. Bentley ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L21/30604 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66666

Abstract: One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.

公开(公告)号：US09640636B1

公开(公告)日：2017-05-02

申请号：US15171795

申请日：2016-06-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven J. Bentley ,  John H. Zhang ,  Kwan-Yong Lim ,  Hiroaki Niimi

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823487 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7827

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial vertically oriented channel semiconductor structure having a first height above a substrate, forming a sacrificial spacer structure adjacent the initial vertically oriented channel semiconductor structure and, with the sacrificial spacer in position, performing at least one process operation to define a self-aligned bottom source/drain region for the device that is self-aligned with respect to the sacrificial spacer structure, forming an isolation region in the trench and forming a bottom source/drain electrode above the isolation region. The method also includes removing the sacrificial spacer structure and forming a bottom spacer material around the vertically oriented channel semiconductor structure above the bottom source/drain electrode.

公开(公告)号：US09530866B1

公开(公告)日：2016-12-27

申请号：US15097621

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl Radens ,  Steven J. Bentley ,  Brian A. Cohen ,  Kwan-Yong Lim

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L29/66666 ,  B82Y10/00 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/7827

Abstract: Forming a first sidewall spacer adjacent a vertically oriented channel semiconductor structure (“VCS structure’) and adjacent a cap layer, performing at least one planarization process so as to planarize an insulating material and expose an upper surface of the cap layer and an upper surface of the first spacer and removing a portion of the first spacer and an entirety of the cap layer so as to thereby expose an upper surface of the VCS structure and define a spacer/contact cavity above the VCS structure and the first spacer. The method also includes forming a second spacer in the spacer/contact cavity, forming a top source/drain region in the VCS structure and forming a top source/drain contact within the spacer/contact cavity that is conductively coupled to the top source/drain region, wherein the conductive contact physically contacts the second spacer in the spacer/contact cavity.

Abstract translation: 形成与垂直取向的沟道半导体结构（“VCS结构”）相邻并且与覆盖层相邻的第一侧壁间隔物，执行至少一个平坦化处理，以平坦化绝缘材料并暴露盖层的上表面和上表面 并且去除所述第一间隔物的一部分和所述盖层的整体，从而暴露所述VCS结构的上表面并且在所述VCS结构和所述第一间隔物之上限定间隔物/接触腔。 该方法还包括在间隔物/接触腔中形成第二间隔物，在VCS结构中形成顶部源极/漏极区域，并在间隔物/接触腔内形成顶部源极/漏极接触，导电耦合到顶部源极/漏极 区域，其中所述导电接触物质地接触所述间隔件/接触腔中的所述第二间隔件。

公开(公告)号：US10418368B1

公开(公告)日：2019-09-17

申请号：US16031030

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven J. Bentley ,  Bipul C. Paul ,  Steven R. Soss

IPC: H01L27/11 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/768 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08

Abstract: A method for forming a buried local interconnect in a source/drain region is disclosed including, among other things, forming a plurality of VOC structures, forming a first source/drain region between a first pair of the plurality of VOC structures, forming a second source/drain region between a second pair of the plurality of VOC structures, and forming an isolation structure between the first and second source/drain regions. A first trench is formed in the first and second source/drain regions and the isolation structure. A liner layer is formed in the first trench, and a first conductive line is formed in the first trench. A dielectric material is formed above the first conductive line. A first opening is formed in the dielectric material to expose a portion of the first conductive line. A first conductive feature is formed in the first opening contacting the exposed portion of the first conductive line.

公开(公告)号：US10192867B1

公开(公告)日：2019-01-29

申请号：US15888401

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet H. Suvarna ,  Hiroaki Niimi ,  Steven J. Bentley ,  Ali Razavieh

IPC: H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/45 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/285

Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.

公开(公告)号：US20170301776A1

公开(公告)日：2017-10-19

申请号：US15132383

申请日：2016-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Steven J. Bentley ,  Kwan-Yong Lim

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/311 ,  H01L21/28 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/66666 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.

公开(公告)号：US20160254361A1

公开(公告)日：2016-09-01

申请号：US15154495

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L29/49 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/45 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US20160020335A1

公开(公告)日：2016-01-21

申请号：US14334950

申请日：2014-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L29/808 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。