公开(公告)号：US10854669B2

公开(公告)日：2020-12-01

申请号：US16909745

申请日：2020-06-23

Applicant: Infineon Technologies AG

Inventor： Dirk Meinhold ,  Emanuele Bruno Bodini ,  Felix Braun ,  Hermann Gruber ,  Uwe Hoeckele ,  Dirk Offenberg ,  Klemens Pruegl ,  Ines Uhlig

IPC: H01L27/146 ,  H01L27/148

Abstract: Techniques are discloses regarding methods of manufacturing an imager as well as an imager device.

公开(公告)号：US20150235917A1

公开(公告)日：2015-08-20

申请号：US14699704

申请日：2015-04-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Kurt Matoy ,  Hubert Maier ,  Christian Krenn ,  Elfriede Kraxner Wellenzohn ,  Helmut Schoenherr ,  Juergen Steinbrenner ,  Markus Kahn ,  Silvana Fister ,  Christoph Brunner ,  Herbert Gietler ,  Uwe Hoeckele

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/02

CPC classification number: H01L23/3171 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/76801 ,  H01L23/291

Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

Abstract translation: 公开了钝化层和制备钝化层的方法。 在一个实施例中，制造钝化层的方法包括在工件上沉积第一硅基电介质层，第一硅基电介质层包含氮，并在第一硅基电介质层上原位沉积第二硅基电介质层， 所述第二电介质层包含氧。

公开(公告)号：US08927419B2

公开(公告)日：2015-01-06

申请号：US14078104

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Uwe Hoeckele

IPC: H01L21/4763 ,  H01L21/26 ,  H01L21/42 ,  H01L21/768 ,  H01L45/00 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76886 ,  H01L21/0237 ,  H01L21/02444 ,  H01L21/02527 ,  H01L21/02675 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76867 ,  H01L23/53276 ,  H01L45/149 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/81 ,  H01L2924/00

Abstract: A method can be used for locally rendering a carbonic isolating layer conductive. In one embodiment, a laser beam is directed onto the carbonic isolating layer so as to convert amorphous carbon of the carbonic isolating layer into graphite-like carbon. In another embodiment, the carbonic layer is heated so as to form a conducting portion of the layer so that a lateral path through the conducting portion connects two circuit elements of the integrated circuit.

Abstract translation: 一种方法可以用于局部渲染碳隔离层导电。 在一个实施例中，激光束被引导到碳隔离层上，以将碳隔离层的无定形碳转变为石墨状碳。 在另一个实施例中，加热碳层以形成该层的导电部分，使得穿过导电部分的横向路径连接集成电路的两个电路元件。

公开(公告)号：US08815743B2

公开(公告)日：2014-08-26

申请号：US13830185

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC: H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.

Abstract translation: 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层不被沉积在填充材料的侧壁上 所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。 该方法还包括通过使用第二绝缘层密封开口来形成空隙。

公开(公告)号：US20140048940A1

公开(公告)日：2014-02-20

申请号：US14060734

申请日：2013-10-23

Applicant: Infineon Technologies AG

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract translation: 公开了半导体器件和方法。 半导体器件包括具有第一区域和第二区域的衬底以及布置在衬底上的绝缘层。 第一导电层布置在第一区域中的绝缘层中或绝缘层中，并且第二导电层布置在第二区域中的绝缘层中或其上。 第一导电层包括第一导电材料，第二导电层包括第二导电材料，其中第一导电材料不同于第二导电材料。 金属层布置在第一导电层上。

公开(公告)号：US10692921B2

公开(公告)日：2020-06-23

申请号：US16566171

申请日：2019-09-10

Applicant: Infineon Technologies AG

Inventor： Dirk Meinhold ,  Emanuele Bruno Bodini ,  Felix Braun ,  Hermann Gruber ,  Uwe Hoeckele ,  Dirk Offenberg ,  Klemens Pruegl ,  Ines Uhlig

IPC: H01L27/146 ,  H01L27/148

Abstract: Techniques are discloses regarding methods of manufacturing an imager as well as an imager device.

公开(公告)号：US10411060B2

公开(公告)日：2019-09-10

申请号：US15586498

申请日：2017-05-04

Applicant: Infineon Technologies AG

Inventor： Dirk Meinhold ,  Emanuele Bruno Bodini ,  Felix Braun ,  Hermann Gruber ,  Uwe Hoeckele ,  Dirk Offenberg ,  Klemens Pruegl ,  Ines Uhlig

IPC: H01L27/146 ,  H01L27/148

Abstract: Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.

公开(公告)号：US20190112182A1

公开(公告)日：2019-04-18

申请号：US16162026

申请日：2018-10-16

Applicant: Infineon Technologies AG

Inventor： Gerhard Metzger-Brueckl ,  Alfons Dehe ,  Uwe Hoeckele ,  Johann Strasser ,  Arnaud Walther

IPC: B81B7/02 ,  B81C1/00

Abstract: A method for sealing an access opening to a cavity comprises the following steps: providing a layer arrangement having a first layer structure and a cavity arranged adjacent to the first layer structure, wherein the first layer structure has an access opening to the cavity, performing a CVD layer deposition for forming a first covering layer having a layer thickness on the first layer structure having the access opening, and performing an HDP layer deposition with a first and second substep for forming a second covering layer on the first covering layer, wherein the first substep comprises depositing a liner material layer on the first covering layer, wherein the second substep comprises partly backsputtering the liner material layer and furthermore the first covering layer in the region of the access opening, and wherein the first and second substeps are carried out alternately and repeatedly a number of times.

公开(公告)号：US09006898B2

公开(公告)日：2015-04-14

申请号：US14060734

申请日：2013-10-23

Applicant: Infineon Technologies AG

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/66

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract translation: 公开了半导体器件和方法。 半导体器件包括具有第一区域和第二区域的衬底以及布置在衬底上的绝缘层。 第一导电层布置在第一区域中的绝缘层中或绝缘层中，并且第二导电层布置在第二区域中的绝缘层中或其上。 第一导电层包括第一导电材料，第二导电层包括第二导电材料，其中第一导电材料不同于第二导电材料。 金属层布置在第一导电层上。

公开(公告)号：US20140117511A1

公开(公告)日：2014-05-01

申请号：US13664311

申请日：2012-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Kurt Matoy ,  Hubert Maier ,  Christian Krenn ,  Elfriede Kraxner Wellenzohn ,  Helmut Schoenherr ,  Juergen Steinbrenner ,  Markus Kahn ,  Fister Schlemitz Silvana ,  Christoph Brunner ,  Herbert Gietler ,  Uwe Hoeckele

IPC: H01L21/31 ,  H01L29/00

CPC classification number: H01L23/3171 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/76801 ,  H01L23/291

Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

Abstract translation: 公开了钝化层和制备钝化层的方法。 在一个实施例中，制造钝化层的方法包括在工件上沉积第一硅基电介质层，第一硅基电介质层包含氮，并在第一硅基电介质层上原位沉积第二硅基电介质层， 所述第二电介质层包含氧。