公开(公告)号：US20200027752A1

公开(公告)日：2020-01-23

申请号：US16588447

申请日：2019-09-30

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Guido Boenig ,  Niels Oeschler ,  Christian Stahlhut

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/00 ,  H01L23/492

Abstract: A method includes placing a substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the substrate, thereby pressing the substrate onto the first curved surface and bending the substrate, and removing the bended substrate from the first bending tool.

公开(公告)号：US20150091148A1

公开(公告)日：2015-04-02

申请号：US14499737

申请日：2014-09-29

Applicant: Infineon Technologies AG

Inventor： Guido Boenig ,  Olaf Hohlfeld

IPC: H01L23/00 ,  H01L23/24

CPC classification number: H01L23/564 ,  H01L23/053 ,  H01L23/16 ,  H01L23/24 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48096 ,  H01L2224/48105 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4909 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module has a carrier, a semiconductor chip mounted on the carrier, a bond wire, a module housing, and a first sound absorber. The module housing has a housing side wall. The bond wire is arranged in the module housing. At least a section of the first sound absorber is arranged between the semiconductor chip and the housing side wall.

Abstract translation: 半导体模块具有载体，安装在载体上的半导体芯片，接合线，模块壳体和第一吸音体。 模块外壳具有外壳侧壁。 接合线布置在模块外壳中。 第一吸声器的至少一部分布置在半导体芯片和壳体侧壁之间。

公开(公告)号：US20230077384A1

公开(公告)日：2023-03-16

申请号：US17942317

申请日：2022-09-12

Applicant: Infineon Technologies AG

Inventor： Marco Ludwig ,  Guido Boenig

IPC: H01L23/16 ,  H01L25/065 ,  H01L25/18

Abstract: A power semiconductor module arrangement includes at least one substrate comprising a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer; at least one semiconductor body arranged on the first metallization layer; a housing at least partly enclosing the substrate, the housing comprising sidewalls; and at least one press-on pin, wherein each press-on pin is arranged either on the substrate or on one of the at least one semiconductor body and extends from the substrate or the respective semiconductor body in a vertical direction that is perpendicular to a top surface of the substrate, and each press-on pin is mechanically coupled to at least one sidewall of the housing by means of a bar, each bar extending horizontally between the respective press-on pin and sidewall, and parallel to the top surface of the substrate.

公开(公告)号：US10475668B2

公开(公告)日：2019-11-12

申请号：US16021619

申请日：2018-06-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Guido Boenig ,  Niels Oeschler ,  Christian Stahlhut

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/00 ,  H01L23/492

Abstract: A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.

公开(公告)号：US20190006193A1

公开(公告)日：2019-01-03

申请号：US16021619

申请日：2018-06-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Guido Boenig ,  Niels Oeschler ,  Christian Stahlhut

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/492

CPC classification number: H01L21/4878 ,  H01L23/3735 ,  H01L23/492 ,  H01L24/75 ,  H01L2224/79315 ,  H01L2924/3511

Abstract: A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.

公开(公告)号：US10096584B2

公开(公告)日：2018-10-09

申请号：US15337733

申请日：2016-10-28

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Guido Boenig ,  Irmgard Escher-Poeppel ,  Edward Fuergut ,  Martin Gruber ,  Thorsten Meyer

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/50 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L21/60

Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.

公开(公告)号：US20170125395A1

公开(公告)日：2017-05-04

申请号：US15337733

申请日：2016-10-28

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Guido Boenig ,  Irmgard Escher-Poeppel ,  Edward Fuergut ,  Martin Gruber ,  Thorsten Meyer

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/14 ,  H01L21/50 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L23/142 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L2021/60015 ,  H01L2021/60022 ,  H01L2021/60277 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/214 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10344 ,  H01L2924/1301 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/85399

Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.

公开(公告)号：US20140035117A1

公开(公告)日：2014-02-06

申请号：US13932531

申请日：2013-07-01

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Guido Boenig ,  Uwe Jansen

IPC: H01L23/24

CPC classification number: H01L23/24 ,  H01L23/291 ,  H01L23/58 ,  H01L24/42 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module includes an electrically conductive lower contact piece and an electrically conductive upper contact piece spaced apart from one another in a vertical direction. The module further includes a semiconductor chip having a first load connection and a second load connection. The semiconductor chip is electrically conductively connected by the second load connection to the lower contact piece, and electrically conductively connected to the upper contact piece by at least one bonding wire bonded to the first load connection. An explosion protection means is arranged between the first load connection and the upper contact piece and into which each of the bonding wires is embedded over at least 80% or over at least 90% of its length.

Abstract translation: 半导体模块包括导电下接触片和在垂直方向上彼此间隔开的导电上接触片。 该模块还包括具有第一负载连接和第二负载连接的半导体芯片。 半导体芯片通过第二负载连接导电连接到下接触片，并且通过至少一个接合到第一负载连接的接合线而导电地连接到上接触片。 防爆装置设置在第一负载连接件和上接触片之间，每个接合线在其长度至少80％或以上至少80％的范围内被嵌入其中。

公开(公告)号：US10600658B2

公开(公告)日：2020-03-24

申请号：US16588447

申请日：2019-09-30

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Guido Boenig ,  Niels Oeschler ,  Christian Stahlhut

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/492 ,  H01L23/00

Abstract: A method includes placing a substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the substrate, thereby pressing the substrate onto the first curved surface and bending the substrate, and removing the bended substrate from the first bending tool.

公开(公告)号：US09214432B2

公开(公告)日：2015-12-15

申请号：US14499737

申请日：2014-09-29

Applicant: Infineon Technologies AG

Inventor： Guido Boenig ,  Olaf Hohlfeld

IPC: H01L23/00 ,  H01L23/24 ,  H01L23/053 ,  H01L23/16

CPC classification number: H01L23/564 ,  H01L23/053 ,  H01L23/16 ,  H01L23/24 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48096 ,  H01L2224/48105 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4909 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module has a carrier, a semiconductor chip mounted on the carrier, a bond wire, a module housing, and a first sound absorber. The module housing has a housing side wall. The bond wire is arranged in the module housing. At least a section of the first sound absorber is arranged between the semiconductor chip and the housing side wall.

Abstract translation: 半导体模块具有载体，安装在载体上的半导体芯片，接合线，模块壳体和第一吸音体。 模块外壳具有外壳侧壁。 接合线布置在模块外壳中。 第一吸声器的至少一部分布置在半导体芯片和壳体侧壁之间。