公开(公告)号：US20170005136A1

公开(公告)日：2017-01-05

申请号：US15122129

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Christopher J. WIEGAND ,  Md Tofizur RAHMAN ,  Oleg GOLONZKA ,  Anant H. JAHAGIRDAR ,  Mengcheng LU

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe techniques and configurations associated with modulation of magnetic properties through implantation. In one embodiment, a method includes providing a substrate having an integrated circuit (IC) structure disposed on the substrate, the IC structure including a magnetizable material, implanting at least a portion of the magnetizable material with a dopant and magnetizing the magnetizable material, wherein said magnetizing is inhibited in the implanted portion of the magnetizable material. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了通过植入调制磁性能的技术和配置。 在一个实施例中，一种方法包括提供具有设置在基板上的集成电路（IC）结构的基板，该IC结构包括可磁化材料，用掺杂剂注入至少一部分可磁化材料并使可磁化材料磁化，其中 在可磁化材料的注入部分中抑制了磁化。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20190393336A1

公开(公告)日：2019-12-26

申请号：US16481028

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Jeffrey S. LEIB ,  Daniel B. BERGSTROM ,  Christopher J. WIEGAND

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/02

Abstract: Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and semiconductor structures having wrap-around metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. The metallic contact material has a total atomic composition including 95% or greater of a single metal species.

公开(公告)号：US20190140166A1

公开(公告)日：2019-05-09

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahhir GHANI ,  Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US20190027537A1

公开(公告)日：2019-01-24

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. WIEGAND ,  Oleg GOLONZKA ,  MD Tofizur RAHMAN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Tahir GHANI ,  Satyarth SURI

IPC: H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  H01L23/528 ,  H01L43/02 ,  H01L23/532 ,  H01L43/12 ,  H01L21/768 ,  H01F41/32

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/32 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L27/226 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of dielectric layer above a substrates, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20180322994A1

公开(公告)日：2018-11-08

申请号：US15773339

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Daniel B. BERGSTROM

IPC: H01F10/32 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F41/32

CPC classification number: H01F10/3254 ,  G11C11/161 ,  H01F10/3272 ,  H01F41/32 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the disclosure are directed to a magnetic tunneling junction (MTJ) that includes a diffusion barrier. The diffusion barrier can be disposed between two ferromagnetic layers of the MTJ. More specifically, the diffusion barrier can be disposed between a first ferromagnetic layer, which is adjacent to a natural antiferromagnetic layer, and a second ferromagnetic layer; the first and second ferromagnetic layers and the diffusion barrier being part of a synthetic antiferromagnet. The diffusion barrier can be made of a refractory metal, such as tantalum. The diffusion barrier acts as a barrier for manganese diffusion from the natural antiferromagnetic layer into the synthetic antiferromagnet and other higher layers of the MTJ.

公开(公告)号：US20160372377A1

公开(公告)日：2016-12-22

申请号：US15221515

申请日：2016-07-27

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。

公开(公告)号：US20150079776A1

公开(公告)日：2015-03-19

申请号：US14548215

申请日：2014-11-19

Applicant: Intel Corporation

Inventor： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8234 ,  H01L21/28

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。

公开(公告)号：US20240347394A1

公开(公告)日：2024-10-17

申请号：US18757060

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/66477 ,  H10B10/12

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US20200235014A1

公开(公告)日：2020-07-23

申请号：US16844588

申请日：2020-04-09

Applicant: Intel Corporation

Inventor： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US20190378972A1

公开(公告)日：2019-12-12

申请号：US16463326

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32

Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.