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    Memory system
    1.
    发明授权
    Memory system 有权

    公开(公告)号：US12170118B2

    公开(公告)日：2024-12-17

    申请号：US18088129

    申请日：2022-12-23

    Applicant: Kioxia Corporation

    Inventor： Yoshihisa Kojima ,  Shunichi Igahara ,  Toshikatsu Hida

    IPC: G11C8/00 ,  G11C16/16 ,  G11C16/34

    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a first block that includes first and second sub-blocks. The memory controller instructs the non-volatile memory to execute a data erase process in units of sub-blocks on data stored in the non-volatile memory. In response to a first value corresponding to the first sub-block having reached a first threshold value, the memory controller reads first data from the first sub-block, executes an error correction process on the first data read from the first sub-block, and writes the first data on which the error correction process has been executed into the non-volatile memory.

    Memory system and memory system control method
    4.
    发明授权
    Memory system and memory system control method 有权

    公开(公告)号：US11954357B2

    公开(公告)日：2024-04-09

    申请号：US17468895

    申请日：2021-09-08

    Applicant: Kioxia Corporation

    Inventor： Takehiko Amaki ,  Shunichi Igahara ,  Toshikatsu Hida ,  Yoshihisa Kojima ,  Riki Suzuki

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0679

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

    Memory system and memory control method
    5.
    发明授权
    Memory system and memory control method 有权

    公开(公告)号：US11940871B2

    公开(公告)日：2024-03-26

    申请号：US17895465

    申请日：2022-08-25

    Applicant: KIOXIA CORPORATION

    Inventor： Yuki Mandai ,  Shuou Nomura ,  Ryo Yamaki ,  Toshikatsu Hida

    IPC: G06F11/10 ,  G11C16/08 ,  G11C16/26

    CPC classification number: G06F11/1024 ,  G11C16/08 ,  G11C16/26

    Abstract: A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

    MEMORY SYSTEM
    7.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20230122474A1

    公开(公告)日：2023-04-20

    申请号：US18086206

    申请日：2022-12-21

    Applicant: KIOXIA CORPORATION

    Inventor： Noboru Okamoto ,  Toshikatsu Hida

    IPC: G06F11/10 ,  G11C16/26 ,  G11C16/20 ,  G11C16/04

    Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

    Memory system
    8.
    发明授权
    Memory system 有权

    公开(公告)号：US11086718B2

    公开(公告)日：2021-08-10

    申请号：US16806131

    申请日：2020-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

    IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

    Memory system and control method
    9.
    发明授权
    Memory system and control method 有权

    公开(公告)号：US11789643B2

    公开(公告)日：2023-10-17

    申请号：US17685229

    申请日：2022-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Suguru Nishikawa ,  Toshikatsu Hida ,  Shunichi Igahara ,  Takehiko Amaki

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0679

    Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.

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