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    METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING THIN FILM TRANSISTORS INCLUDING OXIDE SEMICONDUCTORS
    2.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING THIN FILM TRANSISTORS INCLUDING OXIDE SEMICONDUCTORS 审中-公开

    公开(公告)号：US20190067453A1

    公开(公告)日：2019-02-28

    申请号：US16114614

    申请日：2018-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Kevin J. Torek

    IPC: H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

    Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

    Methods of forming capacitors
    7.
    发明授权
    Methods of forming capacitors 有权
    形成电容器的方法

    公开(公告)号：US09196673B2

    公开(公告)日：2015-11-24

    申请号：US14147895

    申请日：2014-01-06

    Applicant: Micron Technology, Inc.

    Inventor： Gurpreet Lugani ,  Kevin J. Torek

    IPC: H01L21/20 ,  H01L21/302 ,  H01L21/461 ,  H01L49/02 ,  H01L27/108 ,  H01L21/311

    CPC classification number: H01L27/10852 ,  H01G4/005 ,  H01G4/008 ,  H01G4/06 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32137 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/91

    Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

    Abstract translation: 形成电容器的方法包括在支撑材料内提供第一电容器电极。 第一电容器电极含有TiN，载体材料含有多晶硅。 使用含硫和含氟蚀刻化学法，相对于含TiN的第一电容器电极，选择性地对含多晶硅的支撑材料进行干式各向异性蚀刻。 在第一电容器电极的侧壁上形成电容器电介质，并且在电容器电介质上形成第二电容器电极。 公开了另外的方法。

    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
    9.
    发明申请
    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors 有权

    公开(公告)号：US20230014320A1

    公开(公告)日：2023-01-19

    申请号：US17947401

    申请日：2022-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC: H01L27/12 ,  H01L21/84

    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

    Array of vertical transistors and method used in forming an array of vertical transistors
    10.
    发明授权
    Array of vertical transistors and method used in forming an array of vertical transistors 有权

    公开(公告)号：US11488981B2

    公开(公告)日：2022-11-01

    申请号：US16934607

    申请日：2020-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC: H01L27/12 ,  H01L21/84 ,  H01L27/13

    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

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