公开(公告)号：US12236466B2

公开(公告)日：2025-02-25

申请号：US17176952

申请日：2021-02-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carla L. Christensen ,  Bethany M. Grentz ,  Xiao Li ,  Sumana Adusumilli ,  Libo Wang

IPC: G06Q30/0601 ,  G06T19/00

Abstract: A size comparison system may generate a size comparison by determining a size of an item based on extracted size data corresponding to the item. A comparison item is selected and the size comparison is generated between the item and the comparison item based on the size of the item. A visual rendering of the item and the comparison item is generated based on the size comparison and is displayed to a user.

公开(公告)号：US20240109560A1

公开(公告)日：2024-04-04

申请号：US18533006

申请日：2023-12-07

Applicant: Micron Technology, Inc.

Inventor： Amy Rae Griffin ,  Xiao Li ,  Maria Pat F. Chavarria ,  Alpha Chavez Labiano

IPC: B60W60/00 ,  B60W30/14 ,  B60W30/16

CPC classification number: B60W60/0016 ,  B60W30/143 ,  B60W30/16 ,  B60W2556/45

Abstract: Systems, methods, and apparatus related to cruise control for a vehicle. In one approach, speed for a first vehicle is controlled in a first mode using data from sensors. The speed is controlled while keeping at least a minimum distance from a second vehicle being followed by the first vehicle. In response to determining that data from the sensors is not usable to control the first vehicle (e.g., the data cannot be used to measure the minimum distance), the first vehicle changes from the first mode to a second mode. In the second mode, the first vehicle maintains a constant speed and/or obtains additional data from sensors and/or computing devices located externally to the first vehicle. In another approach, the additional data can additionally or alternatively be obtained from a mobile device of a passenger of the first vehicle. The additional data is used to maintain a safe minimum distance from the second vehicle.

公开(公告)号：US20240049468A1

公开(公告)日：2024-02-08

申请号：US18381791

申请日：2023-10-19

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

公开(公告)号：US20230397424A1

公开(公告)日：2023-12-07

申请号：US18324084

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Everett A. McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Christopher R. Ritchie ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Sijia Yu ,  Naiming Liu

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A microelectronic device comprises a stack structure, a memory pillar, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The memory pillar extends through the stack structure and defines memory cells at intersections of the memory pillar and the conductive structures. The boron-containing material is on at least a portion of the conductive structures of the stack structure. Related methods and electronic systems are also described.

公开(公告)号：US20230395463A1

公开(公告)日：2023-12-07

申请号：US18454703

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/373 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/44 ,  H01L25/50 ,  H01L21/563 ,  H01L24/83 ,  H01L23/3675 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0657 ,  H01L23/3736 ,  H01L24/73 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/3128 ,  H01L2924/156 ,  H01L2924/1815 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/17519 ,  H01L2224/2939 ,  H01L24/29 ,  H01L24/33 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2224/83104 ,  H01L2224/1329

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US11594462B2

公开(公告)日：2023-02-28

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20220254727A1

公开(公告)日：2022-08-11

申请号：US17660669

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US20210193607A1

公开(公告)日：2021-06-24

申请号：US16719643

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Christopher Glancey ,  Koustav Sinha ,  Xiao Li

IPC: H01L23/00 ,  B23K1/19

Abstract: Solder joints comprising two different solder materials having different melting points, an outer solder material extending over an inner solder material bonded to a conductive pad, the inner solder material having a lower melting point than a melting point of the outer solder material and being in a solid state at substantially ambient temperature. A metal material having a higher melting point than a melting point of either solder material may coat at least a portion of the inner solder material. Microelectronic components, assemblies and electronic systems incorporating the solder joints, as well as processes for forming and repairing the solder joints are also disclosed.

公开(公告)号：US10916487B2

公开(公告)日：2021-02-09

申请号：US16505434

申请日：2019-07-08

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/427 ,  H01L23/42 ,  H01L25/065 ,  H01L23/46 ,  H01L23/473 ,  H01L23/433

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

公开(公告)号：US10804256B2

公开(公告)日：2020-10-13

申请号：US16106190

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367

Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.