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公开(公告)号：US20240126690A1
公开(公告)日：2024-04-18
申请号：US18395363
申请日：2023-12-22
发明人： Kishore Kumar Muchherla , Peter Feeley , Ashutosh Malshe , Daniel J. Hubbard , Christopher S. Hale , Kevin R. Brandt , Sampath K. Ratnam , Yun Li , Marc S. Hamilton
IPC分类号： G06F12/02 , G06F3/06 , G06F12/00 , G06F12/06 , G06F12/0891
CPC分类号： G06F12/0253 , G06F3/0629 , G06F3/0634 , G06F3/064 , G06F3/0688 , G06F3/0689 , G06F12/00 , G06F12/0646 , G06F12/0891 , G11C11/5621
摘要： A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
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公开(公告)号：US20240069745A1
公开(公告)日：2024-02-29
申请号：US17897784
申请日：2022-08-29
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0611 , G06F3/0629 , G06F3/0679
摘要： An example method of performing read operation comprises: receiving a read request with respect to a set of memory cells of a memory device; determining a value of a media endurance metric of the set of memory cells; determining a programing temperature associated with the set of memory cells; determining a current operating temperature of the memory device; determining a voltage adjustment value based on the value of the media endurance metric, the programming temperature, and the current operating temperature; adjusting, by the voltage adjustment value, a bitline voltage applied to a bitline associated with the set of memory cells; and performing, using the adjusted bitline voltage, a read operation with respect to the set of memory cells.
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公开(公告)号：US20240062835A1
公开(公告)日：2024-02-22
申请号：US17891859
申请日：2022-08-19
发明人： Vamsi Pavan Rayaprolu , Christopher M. Smitchger , James Fitzpatrick , Patrick R. Khayat , Sampath K. Ratnam
CPC分类号： G11C16/34 , G11C16/26 , G11C16/0483
摘要： A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event and, responsive to the occurrence of the data integrity check trigger event, identifies a memory die of a plurality of memory dies. The processing device further associates each segment of the identified memory die with a respective group of a plurality of groups, each group representing one or more of a plurality of error mechanisms, and determines one or more respective adaptive scan frequencies for the identified memory die based on statistics of the segments associated with each respective group.
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公开(公告)号：US11868202B2
公开(公告)日：2024-01-09
申请号：US17946328
申请日：2022-09-16
发明人： Qisong Lin , Vamsi Pavan Rayaprolu , Jiangang Wu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Shao Chun Shi
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0751
摘要： A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.
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公开(公告)号：US11710527B2
公开(公告)日：2023-07-25
申请号：US17868685
申请日：2022-07-19
发明人： Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Peter Feeley , Sampath K. Ratnam , Sivagnanam Parthasarathy , Qisong Lin , Shane Nowell , Mustafa N. Kaynak
IPC分类号： G11C16/34 , G11C16/10 , G11C16/14 , G11C29/00 , G06F11/07 , G11C16/26 , G06F3/06 , G11C16/04
CPC分类号： G11C16/34 , G06F3/0619 , G06F3/0634 , G06F3/0679 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C29/00 , G11C29/84 , G11C16/0483 , G11C2207/229 , G11C2207/2272 , G11C2207/2281
摘要： A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
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公开(公告)号：US11704179B2
公开(公告)日：2023-07-18
申请号：US17452930
申请日：2021-10-29
发明人： Vamsi Pavan Rayaprolu , Harish R. Singidi , Ashutosh Malshe , Sampath K. Ratnam , Qisong Lin , Kishore Kumar Muchherla
CPC分类号： G06F11/076 , G06F3/064 , G06F3/0616 , G06F3/0646 , G06F3/0653 , G06F3/0679 , G06F11/0757 , G06F11/1068 , G06F11/3058
摘要： Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.
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公开(公告)号：US11688483B2
公开(公告)日：2023-06-27
申请号：US17521785
申请日：2021-11-08
发明人： Kishore Kumar Muchherla , Sampath K. Ratnam , Scott A. Stoller , Preston A. Thomson , Kevin R. Brandt , Marc S. Hamilton , Christopher S. Hale
摘要： A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.
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公开(公告)号：US11662786B2
公开(公告)日：2023-05-30
申请号：US17447167
申请日：2021-09-08
IPC分类号： G11C11/06 , G06F1/20 , G06F1/3234 , G11C11/56
CPC分类号： G06F1/206 , G06F1/3275 , G11C11/5628
摘要： A processing device in a memory sub-system stores data at a first voltage level in a memory cell in a first segment of the memory sub-system, and determines a temperature change between a current temperature associated with the memory cell and a new temperature. The processing device further determines a voltage level read from the memory cell at the new temperature, determines a difference between the voltage level read from the memory cell and the first voltage level, and determines a temperature compensation value based on the difference between the voltage level read from the memory cell and the first voltage level in view of the temperature change.
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公开(公告)号：US20230110545A1
公开(公告)日：2023-04-13
申请号：US18079843
申请日：2022-12-12
发明人： Kishore Kumar Muchherla , Harish R. Singidi , Vamsi Pavan Rayaprolu , Ashutosh Malshe , Sampath K. Ratnam
摘要： A request to perform a secure erase operation for a memory component can be received. A voltage level of a pass voltage that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied during a program operation to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can exceed the pass voltage applied to the unselected wordlines of the memory component during the read operation.
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公开(公告)号：US20220391127A1
公开(公告)日：2022-12-08
申请号：US17339660
申请日：2021-06-04
发明人： Tawalin Opastrakoon , Renato C. Padilla , Michael G. Miller , Christopher M. Smitchger , Gary F. Besinga , Sampath K. Ratnam , Vamsi Pavan Rayaprolu
IPC分类号： G06F3/06
摘要： A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.
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