公开(公告)号：US10325859B1

公开(公告)日：2019-06-18

申请号：US15944233

申请日：2018-04-03

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Manuel Aldrete

IPC: H01L23/538 ,  H01L23/552 ,  H01L25/16

Abstract: Some features pertain to a stacked package apparatus that includes a shield at least partially surrounding the apparatus, a first substrate including a plurality of first pads, the plurality of first pads coupled to the shield, and a second substrate, the second substrate over the first substrate and coupled to the first substrate, the second substrate including a plurality of second pads, the plurality of second pads coupled to the shield.

公开(公告)号：US20170271266A1

公开(公告)日：2017-09-21

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

公开(公告)号：US09768108B2

公开(公告)日：2017-09-19

申请号：US14859318

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Milind Pravin Shah ,  Dwayne Richard Shirley

IPC: H01L23/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

公开(公告)号：US20160148864A1

公开(公告)日：2016-05-26

申请号：US14703617

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  David Fraser Rae ,  Manuel Aldrete ,  Vladimir Noveski ,  Chin-Kwan Kim

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L24/92 ,  H01L23/49811 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/152

Abstract: Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second package substrate, and a solder joint structure coupled to the first package substrate and the second package substrate. The solder joint structure includes a solder comprising a first melting point temperature, and a conductive material comprising a second melting point temperature that is less than the first melting point temperature. In some implementations, the conductive material is one of at least a homogeneous material and/or a heterogeneous material. In some implementations, the conductive material includes a first electrically conductive material and a second material. The conductive material is an electrically conductive material.

Abstract translation: 一些特征涉及集成电路器件，其包括第一封装衬底，耦合到第一封装衬底的第一管芯，第二封装衬底以及耦合到第一封装衬底和第二封装衬底的焊点结构。 焊接结构包括包含第一熔点温度的焊料和包含小于第一熔点温度的第二熔点温度的导电材料。 在一些实施方案中，导电材料是至少均质材料和/或异质材料之一。 在一些实施方案中，导电材料包括第一导电材料和第二材料。 导电材料是导电材料。

公开(公告)号：US20150179590A1

公开(公告)日：2015-06-25

申请号：US14251518

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Manuel Aldrete ,  Milind Pravin Shah

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/03 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2924/12042 ,  H01L2924/381 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

Abstract translation: 一些新颖的特征涉及包括基板，第一通孔和第一凸块焊盘的集成装置。 第一个通孔穿过基板。 第一个通孔具有第一通孔尺寸。 第一凸块焊盘位于基板的表面上。 第一碰撞焊盘耦合到第一通孔。 第一凸块焊盘具有等于或小于第一通孔尺寸的第一焊盘尺寸。 在一些实施方案中，集成器件包括第二通孔和第二凸点焊盘。 第二个通孔穿过基板。 第二通孔具有第二通孔尺寸。 第二凸点焊盘位于基板的表面上。 第二凸点焊盘耦合到第二通孔。 第二凸块焊盘具有等于或小于第二通孔尺寸的第二焊盘尺寸。

公开(公告)号：US10431511B2

公开(公告)日：2019-10-01

申请号：US15584000

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Shu Zhang ,  Bonhoon Koo ,  Manuel Aldrete ,  Jie Fu ,  Chin-Kwan Kim ,  Babak Nejati ,  Husnu Ahmet Masaracioglu

IPC: H01L23/12 ,  H01L23/66 ,  H01L23/498 ,  H01L23/552

Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.

公开(公告)号：US10319694B2

公开(公告)日：2019-06-11

申请号：US15233902

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik Kim ,  Jie Fu ,  Manuel Aldrete ,  Jonghae Kim ,  Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Mario Francisco Velez

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.

公开(公告)号：US20160322332A1

公开(公告)日：2016-11-03

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

Abstract translation: 一些特征涉及包括再分配部分，耦合到再分配部分的第一裸片，耦合到再分配部分的核心层以及封装第一裸片和核心层的封装层的封装。 再分配部分包括第一电介质层。 核心层具有比封装层更高的杨氏模量。 在一些实施方案中，芯层包括玻璃纤维（例如，芯层是玻璃增强介电层）。 在一些实施方案中，核心层具有约至少15吉帕斯卡（Gpa）的杨氏模量。 在一些实施方案中，第一管芯包括前侧和后侧，其中第一管芯的前侧连接到再分配部分。 在一些实施方案中，第一电介质层是可光致成像电介质（PID）层。

公开(公告)号：US10325855B2

公开(公告)日：2019-06-18

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

公开(公告)号：US09806063B2

公开(公告)日：2017-10-31

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.