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公开(公告)号：US20180019256A1
公开(公告)日：2018-01-18
申请号：US15332429
申请日：2016-10-24
发明人： Fumitaka AMANO , Takashi ARAI , Genta MIZUNO , Shigehisa INOUE , Naoki TAKEGUCHI , Takashi HAMAYA
IPC分类号： H01L29/423 , H01L23/522 , H01L23/532 , H01L21/768
CPC分类号： H01L27/11582 , H01L21/28562 , H01L21/76831 , H01L21/76846 , H01L21/76876 , H01L21/76877 , H01L21/76879 , H01L23/53266 , H01L27/11565 , H01L27/1157
摘要： Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.
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2.发明申请公开(公告)号：US20170373079A1
公开(公告)日：2017-12-28
申请号：US15483862
申请日：2017-04-10
IPC分类号： H01L27/11556 , H01L27/11524 , H01L21/768 , H01L23/532 , H01L27/11582 , H01L27/1157
CPC分类号： H01L27/11556 , H01L21/28282 , H01L21/76847 , H01L23/53266 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.
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3.发明公开公开(公告)号：US20230402387A1
公开(公告)日：2023-12-14
申请号：US17806415
申请日：2022-06-10
IPC分类号： H01L23/535 , H01L23/528 , H01L23/532 , H01L27/11556 , H01L27/11582
CPC分类号： H01L23/535 , H01L23/5283 , H01L23/53266 , H01L27/11556 , H01L27/11582
摘要： A three dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures vertically extending through the alternating stack; and a backside trench fill structure. The backside trench fill structure includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure may include a tapered metallic nitride liner and at least one core fill conductive material portion. Alternatively, the backside contact via structure may include a tungsten nitride liner, a metallic nitride liner other than tungsten nitride, and at least one core fill conductive material portion.
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4.发明申请公开(公告)号：US20200258909A1
公开(公告)日：2020-08-13
申请号：US16860358
申请日：2020-04-28
发明人： Fumitaka AMANO
IPC分类号： H01L27/11582 , H01L29/45 , H01L21/768 , H01L23/485 , H01L21/265 , H01L27/11568 , H01L27/11521 , H01L27/11526 , H01L27/11573 , H01L29/167 , H01L27/11556
摘要： A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.
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5.发明申请公开(公告)号：US20180331118A1
公开(公告)日：2018-11-15
申请号：US15593916
申请日：2017-05-12
发明人： Fumitaka AMANO
IPC分类号： H01L27/11582 , H01L23/522 , H01L23/528 , H01L27/11556 , H01L29/167 , H01L27/11573 , H01L27/11526 , H01L27/11521 , H01L27/11568 , H01L23/532 , H01L21/768 , H01L21/265
CPC分类号： H01L27/11582 , H01L21/26513 , H01L21/76802 , H01L21/76841 , H01L21/76846 , H01L21/76855 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53209 , H01L23/53261 , H01L23/53266 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573 , H01L29/167 , H01L29/456
摘要： A semiconductor structure includes a doped semiconductor material portion, a metal-semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen-containing material layer containing nitrogen and an element selected from silicon or boron.
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公开(公告)号：US20240282710A1
公开(公告)日：2024-08-22
申请号：US18359610
申请日：2023-07-26
发明人： Linghan CHEN , Fumitaka AMANO
IPC分类号： H01L23/532 , H01L21/768 , H01L23/522
CPC分类号： H01L23/5329 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H10B43/20 , H10B51/20 , H10B63/10
摘要： A device structure includes a first dielectric material layer, a first conductive interconnect structure embedded in the first dielectric material layer and including a first metallic barrier liner and a first metal fill material portion having a top surface within a first horizontal plane, where the first metallic barrier liner laterally surrounds the first metal fill material portion and has a top surface below the first horizontal plane such that a moat-shaped divot is located between the first metal fill material portion and the first dielectric material layer, a divot-fill dielectric portion located in the moat-shaped divot and contacting the top surface of the first metallic barrier liner, a second dielectric material layer overlying the first dielectric material layer, and a second conductive interconnect structure embedded in the second dielectric material layer and contacting at least a segment of the top surface of the first metal fill material portion.
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公开(公告)号：US20230130849A1
公开(公告)日：2023-04-27
申请号：US18059698
申请日：2022-11-29
发明人： Takashi YAMAHA , Tatsuya HINOUE , Fumitaka AMANO
IPC分类号： H01L23/535 , H01L23/532 , H01L27/11556 , H01L27/11582 , H01L21/768
摘要： A metal interconnect assembly includes a first metal interconnect structure, and a second metal interconnect structure embedded in a second dielectric material layer and containing a metal line portion having a top surface located within a first horizontal plane and having a bottom surface located within a second horizontal plane, and further containing a metal via portion adjoined to a bottom of the metal line portion and contacting a top surface of the first metal interconnect structure. The second metal interconnect structure contains a metallic liner including a first metallic material that includes an entire volume of the metal via portion and an outer part of the metal line portion, and a metallic fill material portion contains a second metallic material that includes an inner part of the metal line portion, does not contact and is spaced from the second dielectric material layer by the metallic liner.
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公开(公告)号：US20180033646A1
公开(公告)日：2018-02-01
申请号：US15730045
申请日：2017-10-11
IPC分类号： H01L21/443 , H01L21/3065 , H01L27/108 , H01L21/311 , H01L27/06 , H01L21/768 , H01L21/441 , H01L29/49 , H01L27/105
CPC分类号： H01L27/11563 , H01L21/3065 , H01L21/311 , H01L21/441 , H01L21/443 , H01L21/76871 , H01L27/0688 , H01L27/1052 , H01L27/108 , H01L27/10844 , H01L27/11534 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L29/495 , H01L29/4975
摘要： Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer.
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公开(公告)号：US20170247794A1
公开(公告)日：2017-08-31
申请号：US15219571
申请日：2016-07-26
发明人： Yusuke MUKAE , Fumitaka AMANO , Naoki TAKEGUCHI
IPC分类号： C23C16/455
CPC分类号： C23C16/45529 , C23C16/45551 , C23C28/04 , C23C28/042 , C23C28/42
摘要： A process chamber includes multiple partitions within a single continuous vacuum enclosure. Each of the multiple partitions is defined by respective distinct volumes within the single continuous vacuum enclosure that are connected thereamongst for unhindered movement of a substrate therethrough. The multiple partitions are configured to provide different process gases or purge gases to the substrate as the substrate cycles through the multiple positions. The process can cycle through a first deposition step that deposits a first material on the substrate in a first position and a second deposition step that deposits a second material on the substrate in a second position within each cycle. Alternatively or additionally, the process spaces can include at least one precursor treatment space and at least one reaction space.
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10.发明公开公开(公告)号：US20230403850A1
公开(公告)日：2023-12-14
申请号：US17806406
申请日：2022-06-10
发明人： Fumitaka AMANO , Ryo KAMBAYASHI
IPC分类号： H01L27/11524 , H01L27/11519 , H01L23/48 , H01L27/11556 , H01L27/1157 , H01L27/11565 , H01L27/11582
CPC分类号： H01L27/11524 , H01L27/11519 , H01L23/481 , H01L27/11556 , H01L27/1157 , H01L27/11565 , H01L27/11582
摘要： A three dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures vertically extending through the alternating stack; and a backside trench fill structure. The backside trench fill structure includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure may include a tapered metallic nitride liner and at least one core fill conductive material portion. Alternatively, the backside contact via structure may include a tungsten nitride liner, a metallic nitride liner other than tungsten nitride, and at least one core fill conductive material portion.
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