公开(公告)号：US11942128B2

公开(公告)日：2024-03-26

申请号：US17576047

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Whankyun Kim ,  Jeong-Heon Park ,  Heeju Shin ,  Youngjun Cho ,  Joonmyoung Lee ,  Junho Jeong

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Disclosed is a magnetic memory device including a pinned magnetic pattern and a free magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the pinned magnetic pattern and the free magnetic pattern, a top electrode on the free magnetic pattern, and a capping pattern between the free magnetic pattern and the top electrode. The capping pattern includes a lower capping pattern, an upper capping pattern between the lower capping pattern and the top electrode, a first non-magnetic pattern between the lower capping pattern and the upper capping pattern, and a second non-magnetic pattern between the first non-magnetic pattern and the upper capping pattern. Each of the lower capping pattern and the upper capping pattern includes a non-magnetic metal. The first non-magnetic pattern and the second non-magnetic pattern include different metals from each other.

公开(公告)号：US12286707B2

公开(公告)日：2025-04-29

申请号：US17487088

申请日：2021-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonmyoung Lee ,  Whankyun Kim ,  Jeongheon Park ,  Junho Jeong

IPC: C23C14/56 ,  C23C14/08 ,  C23C16/40 ,  C23C16/54 ,  H01L21/67 ,  H10N50/01

Abstract: An apparatus for manufacturing a semiconductor device includes first and second process chambers in a first row in a first direction, third and fourth process chambers in a second row in the first direction, the third and fourth process chambers being spaced apart from the first and second process chambers in a second direction, and the first and third process chambers being arranged in parallel in the second direction to perform a same process, a load-lock chamber at one side of the first to fourth process chambers in the first direction, and first and second transfer chambers directly connected to each other in a third row in the first direction, the third row being between the first and second rows, and each of the first and second transfer chambers including a transfer unit to transfer a semiconductor substrate between the first to fourth process chambers and the load-lock chamber.

公开(公告)号：US11730064B2

公开(公告)日：2023-08-15

申请号：US16950009

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Chul Lee ,  Whankyun Kim ,  Joonmyoung Lee ,  Junho Jeong

IPC: H10N52/80 ,  G11C11/18 ,  G11C11/16 ,  H10B61/00 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H10B61/22 ,  H10N52/00 ,  H10N52/01

Abstract: A magnetic memory device including a lower electrode on a substrate; a conductive line on the lower electrode; and a magnetic tunnel junction pattern on the conductive line, wherein the conductive line includes a first conductive line adjacent to the magnetic tunnel junction pattern; a second conductive line between the lower electrode and the first conductive line; and a high resistance layer at least partially between the first conductive line and the second conductive line, a resistivity of the second conductive line is lower than a resistivity of the first conductive line, and a resistivity of the high resistance layer is higher than the resistivity of the first conductive line and higher than the resistivity of the second conductive line.

公开(公告)号：US20230180625A1

公开(公告)日：2023-06-08

申请号：US17817441

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonmyoung Lee ,  Junghwan Park ,  Jeong-Heon Park ,  Kyungil Hong

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic memory device includes a first magnetic pattern and a second magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the first magnetic pattern and the second magnetic pattern, a lower electrode between the substrate and the first magnetic pattern, a blocking pattern between the lower electrode and the first magnetic pattern, a metal oxide pattern between the blocking pattern and the first magnetic pattern, and a buffer pattern between the metal oxide pattern and the first magnetic pattern. The lower electrode, the blocking pattern, the metal oxide pattern, and the buffer pattern include first, second, third, and fourth non-magnetic metals, respectively. The metal oxide pattern has an amorphous phase.

公开(公告)号：US20220037586A1

公开(公告)日：2022-02-03

申请号：US17212790

申请日：2021-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Jeong ,  Joonmyoung Lee ,  Whankyun Kim ,  Eunsun Noh ,  Jeongheon Park ,  Wanjin Chung

IPC: H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22

Abstract: Provided is a magnetic memory device. The magnetic memory device may include a magnetic tunnel junction. The magnetic tunnel junction may include a fixed layer, a tunnel barrier layer on the fixed layer, a free layer on the tunnel barrier layer, a protection layer above the free layer, the protection layer comprising an amorphous metal boride, and a capping layer on the protection layer, the capping layer comprising a metal or a metal nitride.

公开(公告)号：US10910552B2

公开(公告)日：2021-02-02

申请号：US16352957

申请日：2019-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonmyoung Lee ,  Yong Sung Park ,  Jeong-Heon Park ,  Hyun Cho ,  Ung Hwan Pi

IPC: H01L43/02 ,  H01L43/10 ,  H01L21/67 ,  G11C14/00 ,  H01L43/12 ,  H01L27/108 ,  H01L27/22 ,  H01L27/11 ,  G11C11/16

Abstract: A magnetic memory device, a method for manufacturing a magnetic memory device, and a substrate treating apparatus, the device including a substrate including a first memory region and a second memory region; a first magnetic tunnel junction pattern on the first memory region, the first magnetic tunnel junction pattern including a first free pattern and a first oxide pattern on the first free pattern; and a second magnetic tunnel junction pattern on the second memory region, the second magnetic tunnel junction pattern including a second free pattern and a second oxide pattern on the second free pattern, wherein a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

公开(公告)号：US10553790B1

公开(公告)日：2020-02-04

申请号：US16440461

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonmyoung Lee ,  Ung Hwan Pi ,  Eunsun Noh ,  Yong Sung Park

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A magnetic memory device includes a first magnetic tunnel junction pattern on a substrate, a second magnetic tunnel junction pattern on the first magnetic tunnel junction pattern, and a conductive line between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern. The conductive line is configured such that a current flowing through the conductive line flows in parallel to an interface between the conductive line and each of the first and second magnetic tunnel junction patterns.

公开(公告)号：US20170092848A1

公开(公告)日：2017-03-30

申请号：US15210627

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngman Jang ,  Joonmyoung Lee ,  Keewon Kim ,  Yong Sung Park

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L43/10

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern including a first free layer, a pinned layer, and a tunnel barrier layer between the first free layer and the pinned layer. The first free layer includes a first free magnetic pattern having a first surface in direct contact with the tunnel barrier layer and a second surface opposite to the first surface, and a second free magnetic pattern in contact with the second surface. The second free magnetic pattern includes iron-nickel (FeNi), and a nickel content of the second free magnetic pattern ranges from about 10 at % to about 30 at %.

公开(公告)号：US11834738B2

公开(公告)日：2023-12-05

申请号：US17956281

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonmyoung Lee ,  Whankyun Kim ,  Eunsun Noh ,  Jeong-heon Park ,  Junho Jeong

IPC: C23C14/54 ,  C23C14/00 ,  G11B5/851 ,  H10B61/00 ,  H10N50/01

CPC classification number: C23C14/541 ,  C23C14/0057 ,  G11B5/851 ,  H10B61/00 ,  H10N50/01

Abstract: A sputtering apparatus including a chamber, a gas supply configured to supply the chamber with a first gas and a second inert gas, the first inert gas and the second inert gas having a first evaporation point and second evaporation point, respectively, a plurality of sputter guns in an upper portion of the chamber, a chuck in a lower portion of the chamber and facing the sputter guns, the chuck configured to accommodate a substrate thereon, and a cooling unit connected to a lower portion of the chuck, the cooling unit configured to cool the chuck to a temperature less than the first evaporation point and greater than the second evaporation point, and a method of fabricating a magnetic memory device may be provided.

公开(公告)号：US11127786B2

公开(公告)日：2021-09-21

申请号：US16556599

申请日：2019-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonmyoung Lee ,  Whankyun Kim ,  Jeong-Heon Park ,  Woo Chang Lim ,  Junho Jeong

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10

Abstract: Disclosed is a magnetic memory device including a line pattern on a substrate, a magnetic tunnel junction pattern on the line pattern, and an upper conductive line that is spaced apart from the line pattern across the magnetic tunnel junction pattern and is connected to the magnetic tunnel junction pattern. The line pattern provides the magnetic tunnel junction pattern with spin-orbit torque. The line pattern includes a chalcogen-based topological insulator.