公开(公告)号：US09559111B2

公开(公告)日：2017-01-31

申请号：US14790969

申请日：2015-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

Abstract translation: 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

公开(公告)号：US09899411B2

公开(公告)日：2018-02-20

申请号：US15414345

申请日：2017-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L21/8247 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/10 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

公开(公告)号：US09130054B2

公开(公告)日：2015-09-08

申请号：US13800872

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC: H01L21/20 ,  H01L29/792 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/1037 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract translation: 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极，该衬底的顶表面上形成有在该衬底中形成的外延层，垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层，设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。

公开(公告)号：US10103170B2

公开(公告)日：2018-10-16

申请号：US15784635

申请日：2017-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun Jang ,  Dongchul Yoo ,  Woojin Jang ,  Jaeyoung Ahn ,  Junkyu Yang

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/28 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L27/11565

Abstract: A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.

公开(公告)号：US20150001609A1

公开(公告)日：2015-01-01

申请号：US14447746

申请日：2014-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewoong Kim ,  Junkyu Yang ,  HongSuk Kim ,  Tae-Jong Han

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/764

Abstract: Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced.

Abstract translation: 提供半导体器件及其形成方法。 半导体器件中的器件隔离结构包括间隙区域。 间隙区域中的真空或空气的介电常数小于氧化物层的介电常数，结果可能减少相邻电池之间的耦合和伴随的干扰。

公开(公告)号：US10109747B2

公开(公告)日：2018-10-23

申请号：US14831449

申请日：2015-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byong-Hyun Jang ,  Juhyung Kim ,  Woonkyung Lee ,  Jaegoo Lee ,  Chaeho Kim ,  Junkyu Yang ,  Phil Ouk Nam ,  Jaeyoung Ahn ,  Kihyun Hwang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/04 ,  H01L29/10 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

公开(公告)号：US09184302B2

公开(公告)日：2015-11-10

申请号：US13765213

申请日：2013-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L23/538

CPC classification number: H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract translation: 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。

公开(公告)号：US09159737B2

公开(公告)日：2015-10-13

申请号：US14447746

申请日：2014-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewoong Kim ,  Junkyu Yang ,  HongSuk Kim ,  Tae-Jong Han

IPC: H01L29/00 ,  H01L27/115 ,  H01L21/764

CPC classification number: H01L27/11521 ,  H01L21/764

Abstract: Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced.

Abstract translation: 提供半导体器件及其形成方法。 半导体器件中的器件隔离结构包括间隙区域。 间隙区域中的真空或空气的介电常数小于氧化物层的介电常数，结果可能减少相邻电池之间的耦合和伴随的干扰。

公开(公告)号：US09076879B2

公开(公告)日：2015-07-07

申请号：US13974122

申请日：2013-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongchul Yoo ,  Phil Ouk Nam ,  Junkyu Yang ,  Woong Lee ,  Woosung Lee ,  JinGyun Kim ,  Daehong Eom

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/7926

Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

Abstract translation: 一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

公开(公告)号：US20130146961A1

公开(公告)日：2013-06-13

申请号：US13765213

申请日：2013-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC: H01L29/788 ,  H01L29/792 ,  H01L23/538

CPC classification number: H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract translation: 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。