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公开(公告)号：US07256121B2
公开(公告)日：2007-08-14
申请号：US11002935
申请日：2004-12-02
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865
摘要： The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
摘要翻译： 本发明提供了一种在半导体衬底100上形成互连的方法。 该方法包括在开口130的内表面上形成开口230，沉积物在开口130的顶部附近形成折入轮廓。 势垒230的一部分被蚀刻，其移除阻挡物230的至少一部分以减少折返轮廓。 蚀刻还去除了开口130底部的阻挡层230的至少一部分。
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公开(公告)号：US07148140B2
公开(公告)日：2006-12-12
申请号：US10901857
申请日：2004-07-28
IPC分类号： H10L21/44
CPC分类号： H01L21/76877 , H01L21/76883
摘要： A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).
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公开(公告)号：US06864108B1
公开(公告)日：2005-03-08
申请号：US10689218
申请日：2003-10-20
CPC分类号： G01K7/36 , G01K7/00 , H01L21/67248
摘要： A coil (50) is placed adjacent to a semiconductor wafer (10). An AC excitation current is used to create a changing electromagnetic field (60) is the wafer (10). The wafer is heated by a heat source (20) and the conductivity of the wafer (10) will change as a function of the wafer temperature. Induced eddy currents will cause the inductance of the coil (50) to change and the temperature of the wafer (10) can be determined by monitoring the inductance of the coil (50).
摘要翻译： 线圈（50）被放置成与半导体晶片（10）相邻。 使用AC激励电流来产生晶片（10）的变化的电磁场（60）。 晶片被热源（20）加热，并且晶片（10）的导电率将随晶片温度的变化而变化。 引起的涡流将导致线圈（50）的电感改变，并且可以通过监测线圈（50）的电感来确定晶片（10）的温度。
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公开(公告)号：US06900127B2
公开(公告)日：2005-05-31
申请号：US10649256
申请日：2003-08-27
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76862 , H01L21/76873
摘要： A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).
摘要翻译： 沟槽（70）形成在电介质层（20）中。 使用物理气相沉积在沟槽中形成第一金属层（80）。 使用化学气相沉积在第一金属层（80）上的沟槽（70）中形成第二金属层（100）。 铜（110）用于通过将铜直接电镀到第二金属（100）上来填充沟槽（70）。
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5.发明授权公开(公告)号：US07179747B2
公开(公告)日：2007-02-20
申请号：US10902243
申请日：2004-07-28
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L23/5329 , H01L21/31116 , H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.
摘要翻译： 本发明的实施例是一种制造集成电路的方法。 该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分 电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。 本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和 金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。
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公开(公告)号：US07115467B2
公开(公告)日：2006-10-03
申请号：US10903712
申请日：2004-07-30
申请人： Sameer Kumar Ajmera , Darius L. Crenshaw , Stephan Grunow , Satyavolu S. Papa Rao , Phillip D. Matz
发明人： Sameer Kumar Ajmera , Darius L. Crenshaw , Stephan Grunow , Satyavolu S. Papa Rao , Phillip D. Matz
IPC分类号： H01L21/8242
CPC分类号： H01L28/75
摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138). A layer of top electrode material (152) is then conformally formed (22) over the layer of capacitor dielectric material (150) to complete the capacitor stack (154).
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7.发明授权公开(公告)号：US07485963B2
公开(公告)日：2009-02-03
申请号：US11614094
申请日：2006-12-21
IPC分类号： H01L23/48 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/76852 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.
摘要翻译： 本发明的实施例是一种制造集成电路的方法。 该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分 电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。 本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和 金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。
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8.发明授权Use of metal phosphorus in metallization of photovoltaic devices and method of fabricating same 有权在金属化光伏器件中使用金属磷及其制造方法公开(公告)号：US09284656B2
公开(公告)日：2016-03-15
申请号：US13154058
申请日：2011-06-06
IPC分类号： C25D3/56 , C25D3/58 , H01L21/288 , H01L23/532 , H01L21/768 , H01L31/0224 , C25D3/38 , C25D3/60 , C25D3/62 , C25D3/64 , C25D5/10 , C25D5/12 , C25D5/50 , C25D7/12 , C25D5/00
CPC分类号： H01L31/022433 , C25D3/38 , C25D3/56 , C25D3/562 , C25D3/567 , C25D3/58 , C25D3/60 , C25D3/62 , C25D3/64 , C25D5/006 , C25D5/10 , C25D5/12 , C25D5/50 , C25D7/12 , H01L21/2885 , H01L21/76841 , H01L23/53238 , H01L31/02168 , H01L31/022425 , H01L31/068 , H01L31/1864 , H01L2924/0002 , Y02E10/50 , H01L2924/00
摘要： A photovoltaic device, such as a solar cell, including a copper-containing-grid metallization structure that contains a metal phosphorus layer as a diffusion barrier is provided. The copper-containing-grid metallization structure includes, from bottom to top, an electroplated metal phosphorus layer that does not include copper or a copper alloy located within a grid pattern formed on a front side surface of a semiconductor substrate, and an electroplated copper-containing layer. A method of forming such a structure is also provided.
摘要翻译： 提供了包含含有金属磷层作为扩散阻挡层的含铜网状金属化结构的太阳能电池等太阳能电池。 含铜网格金属化结构从底部到顶部包括不包括位于半导体衬底的前侧表面上的栅格图案内的铜或铜合金的电镀金属磷层，以及电镀铜 - 含有层。 还提供了一种形成这种结构的方法。
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公开(公告)号：US20120329200A1
公开(公告)日：2012-12-27
申请号：US13165339
申请日：2011-06-21
CPC分类号： H01L31/03845 , B82Y30/00 , C09K13/02 , H01L31/02363 , H01L31/1804 , H01L31/186 , Y02E10/547 , Y02P70/521
摘要： A method of texturing a surface of a crystalline silicon substrate is provided. The method includes immersing a crystalline silicon substrate into an aqueous alkaline etchant solution to form a pyramid shaped textured surface, with (111) faces exposed, on the crystalline silicon substrate. The aqueous alkaline etchant solution employed in the method of the present disclosure includes an alkaline component and a nanoparticle slurry component. Specifically, the aqueous alkaline etchant solution of the present disclosure includes 0.5 weight percent to 5 weight percent of an alkaline component and from 0.1 weight percent to 5 weight percent of a nanoparticle slurry on a dry basis.
摘要翻译： 提供了一种纹理化晶体硅衬底表面的方法。 该方法包括将晶体硅衬底浸入碱性蚀刻剂水溶液中，以形成在晶体硅衬底上（111）面暴露的金字塔形纹理表面。 用于本公开方法的碱性蚀刻剂水溶液包括碱性组分和纳米颗粒淤浆组分。 具体地说，本公开的碱性蚀刻剂水溶液包含0.5重量％至5重量％的碱性组分和0.1重量％至5重量％的基于干基的纳米颗粒浆料。
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10.发明授权Method to improve inductance with a high-permeability slotted plate core in an integrated circuit 有权在集成电路中用高磁导率开槽板芯改善电感的方法公开(公告)号：US07969274B2
公开(公告)日：2011-06-28
申请号：US12202665
申请日：2008-09-02
IPC分类号： H01F5/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01F2017/008 , H01L2924/0002 , H01L2924/3011 , Y10T29/49073 , H01L2924/00
摘要： An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed over or within the first isolation layer (106, 114). The first core plate (104) includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer (108) overlies the first isolation layer and an inductor coil (102) composed of a conductive material layer (118) is formed within the second isolation layer (108). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil (102).
摘要翻译： 公开了一种形成在集成电路（100）中的电感器结构（102），并且包括设置在第一隔离层（106,114）上或第一隔离层（106,114）内的第一隔离层（106）和第一芯板（104）。 第一芯板（104）包括由导电铁磁材料层构成的多个电耦合导电迹线。 第二隔离层（108）覆盖第一隔离层，并且在第二隔离层（108）内形成由导电材料层（118）构成的电感线圈（102）。 可以在线圈上形成另一个芯板。 一个或多个芯板增加电感线圈（102）的电感（L）。
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