公开(公告)号：US08859077B2

公开(公告)日：2014-10-14

申请号：US13028588

申请日：2011-02-16

申请人： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Satoshi Hirano

IPC分类号： B32B3/24 ,  H05K3/46 ,  H05K1/11 ,  H05K3/20

CPC分类号： H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T428/24331 ,  Y10T428/24339

摘要： A plurality of openings are formed in a resin insulation layer on a bottom surface side of a wiring laminate portion which constitutes a multilayer wiring substrate. A plurality of motherboard connection terminals are disposed to correspond to the openings. The motherboard connection terminals are primarily comprised of a copper layer, and peripheral portions of terminal outer surfaces thereof are covered by the outermost resin insulation layer. A dissimilar metal layer made of at least one metal which is lower in etching rate than copper is formed between an inner main surface of the outermost resin insulation layer and peripheral portions of the terminal outer surfaces.

摘要翻译： 在构成多层布线基板的布线层叠体的底面侧的树脂绝缘层上形成有多个开口部。 多个主板连接端子被设置成对应于这些开口。 母板连接端子主要由铜层构成，其端子外表面的周边部分被最外层树脂绝缘层覆盖。 在最外层树脂绝缘层的内主表面和端子外表面的周边部分之间形成由蚀刻速率低于铜的至少一种金属制成的异种金属层。

公开(公告)号：US08707554B2

公开(公告)日：2014-04-29

申请号：US12979474

申请日：2010-12-28

申请人： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Takuya Hando ,  Tatsuya Ito ,  Satoshi Hirano ,  Atsuhiko Sugimoto

发明人： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Takuya Hando ,  Tatsuya Ito ,  Satoshi Hirano ,  Atsuhiko Sugimoto

IPC分类号： H01R9/00 ,  H05K3/00

CPC分类号： H05K1/0298 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/09 ,  H05K1/111 ,  H05K1/113 ,  H05K3/0055 ,  H05K3/3452 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099

摘要： In a build-up step, a plurality of resin insulation layers and a plurality of conductive layers are alternately laminated in multilayer arrangement on a metal foil separably laminated on a side of a base material, thereby forming a wiring laminate portion. In a drilling step, a plurality of openings are formed in an outermost resin insulation layer through laser drilling so as to expose connection terminals. Subsequently, in a desmear step, smears from inside the openings are removed. In a base-material removing step performed after the build-up step, the base material is removed and the metal foil is exposed.

摘要翻译： 在堆积步骤中，将多个树脂绝缘层和多个导电层以多层布置交替层叠在可分离地层叠在基材侧上的金属箔上，从而形成布线层压体部分。 在钻井工序中，通过激光钻孔在最外层的树脂绝缘层上形成多个开口，露出连接端子。 随后，在去污步骤中，去除开口内部的污迹。 在堆积步骤之后执行的基材除去步骤中，除去基材并暴露金属箔。

公开(公告)号：US08581388B2

公开(公告)日：2013-11-12

申请号：US12976427

申请日：2010-12-22

申请人： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Atsuhiko Sugimoto ,  Tatsuya Ito ,  Takuya Hando ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Atsuhiko Sugimoto ,  Tatsuya Ito ,  Takuya Hando ,  Satoshi Hirano

IPC分类号： H01L23/053 ,  H01L21/4763

CPC分类号： H05K3/3452 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09527 ,  H05K2201/099 ,  H05K2203/0346 ,  H05K2203/0369 ,  H01L2924/00

摘要： A multilayered wiring substrate, comprising: a plurality of first main surface side connecting terminals arranged in a first main surface of a stack structure; and a plurality of second main surface side connecting terminals being arranged in a second main surface of the stack structure; wherein a plurality of conductor layers are alternately formed in a plurality of stacked resin insulation layers and are operably connected to each other through via conductors tapered such that diameters thereof are widened toward the first or the second main surface, wherein a plurality of openings are formed in an exposed outermost resin insulation layer in the second main surface, and terminal outer surfaces of the second main surface side connecting terminals arranged to match with the plurality of the openings are positioned inwardly from an outer main surface of the exposed outermost resin insulation layer, and edges of terminal inner surfaces are rounded.

摘要翻译： 一种多层布线基板，包括：布置在堆叠结构的第一主表面中的多个第一主表面侧连接端子; 并且多个第二主表面侧连接端子布置在所述堆叠结构的第二主表面中; 其中多个导体层交替地形成在多个堆叠的树脂绝缘层中，并且通过锥形的通孔导体可操作地连接，使得其直径朝向第一或第二主表面加宽，其中形成多个开口 在第二主表面中暴露的最外层树脂绝缘层中，并且布置成与多个开口相匹配的第二主表面侧连接端子的端子外表面从暴露的最外层树脂绝缘层的外主表面位于内侧， 并且端子内表面的边缘是圆形的。

公开(公告)号：US08450622B2

公开(公告)日：2013-05-28

申请号：US13031735

申请日：2011-02-22

申请人： Shinnosuke Maeda ,  Takuya Torii ,  Tetsuo Suzuki ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Takuya Torii ,  Tetsuo Suzuki ,  Satoshi Hirano

IPC分类号： H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H05K1/11

CPC分类号： H01L21/6835 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/4682 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： A multilayer wiring substrate includes first principal surface side connection terminals arranged on a first principal surface of a stacked configuration; wherein, the first principal surface side connection terminals include an IC chip connection terminal, and a passive element connection terminal; the IC chip connection terminal is located in an opening formed in a resin insulating layer of an uppermost outer layer; the passive element connection terminal is formed of an upper terminal part formed on the resin insulating layer, and a lower terminal part located in an opening formed at a portion of an inner side of the upper terminal part in the resin insulating layer; and, wherein an upper face of the upper terminal part is higher than a reference surface, and an upper face of the IC chip connection terminal and the lower terminal part are identical in height to or lower in height than the reference surface.

摘要翻译： 多层布线基板包括布置在堆叠构造的第一主表面上的第一主表面侧连接端子; 其中，所述第一主面侧连接端子包括IC芯片连接端子和无源元件连接端子; IC芯片连接端子位于形成在最上层外层的树脂绝缘层中的开口中; 无源元件连接端子由形成在树脂绝缘层上的上端子部和位于树脂绝缘层中的上端子部的内侧的开口部的下端子部构成， 并且其中所述上端子部分的上表面高于参考表面，并且所述IC芯片连接端子和所述下端子部分的上表面的高度与所述基准表面的高度相同或更低。

公开(公告)号：US08772643B2

公开(公告)日：2014-07-08

申请号：US13028545

申请日：2011-02-16

申请人： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Satoshi Hirano

IPC分类号： H05K1/09

CPC分类号： H05K3/4682 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/0588 ,  Y10T29/302 ,  Y10T29/49117 ,  H01L2924/00

摘要： A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

摘要翻译： 在布线层叠部的顶面侧的树脂绝缘层上形成有多个开口部，在其底面侧的树脂绝缘层上形成有多个开口部。 多个连接端子被设置成对应于这些开口。 连接端子的端子外表面的外围部分被顶表面侧上的树脂绝缘层覆盖，并且连接端子的端子外表面的周边部分被底表面侧上的树脂绝缘层覆盖。 每个第二主表面侧连接端子在端子外表面的中心具有凹部，并且凹部的最深部相对于端子外表面的周边部位于内侧 。

公开(公告)号：US08658905B2

公开(公告)日：2014-02-25

申请号：US13070094

申请日：2011-03-23

申请人： Shinnosuke Maeda ,  Tatsuya Ito ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Tatsuya Ito ,  Satoshi Hirano

IPC分类号： H05K1/03

CPC分类号： H05K3/244 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/099 ,  H05K2203/0361 ,  H01L2924/00

摘要： In a wiring laminate portion of a multilayer wiring substrate, a solder resist layer having a plurality of openings is disposed on a main surface side of the laminate structure, and connection terminals are embedded in an outermost resin insulation layer in contact with the solder resist layer. Each of the connection terminals comprises a copper layer and a metallic layer formed of at least one type of metal other than copper. A main-surface-side circumferential portion of the copper layer is covered by the solder resist layer. At least a portion of the metallic layer is located in a recess in a main-surface-side central portion of the copper layer. At least a portion of the metallic layer is exposed via a corresponding opening.

摘要翻译： 在多层布线基板的布线层叠部分中，具有多个开口的阻焊层设置在层叠结构的主表面侧，并且连接端子嵌入在与阻焊层接触的最外层树脂绝缘层中 。 每个连接端子包括铜层和由铜以外的至少一种类型的金属形成的金属层。 铜层的主表面侧圆周部分被阻焊层覆盖。 金属层的至少一部分位于铜层的主表面侧中央部的凹部中。 金属层的至少一部分经由相应的开口露出。

公开(公告)号：US08530751B2

公开(公告)日：2013-09-10

申请号：US13195290

申请日：2011-08-01

申请人： Shinnosuke Maeda ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Satoshi Hirano

IPC分类号： H05K1/00

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4015 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/10977 ,  H05K2201/2009 ,  H05K2203/041 ,  H01L2924/00

摘要： A multilayer wiring substrate includes a laminate structure in which resin insulation layers and conductor layers are alternately laminated. The resin insulation layers include first-type resin insulation layers, and second-type resin insulation layers, each of which contains an inorganic material in a larger amount and is smaller in thermal expansion coefficient as compared with first-type resin insulation layers. On a cross section of the laminate structure taken along a thickness direction thereof, the ratio of a total thickness of the second-type resin insulation layers located in an area A2 to a thickness corresponding to the area A2 is greater than the ratio of a total thickness of the second-type resin insulation layers located in an area A1 to a thickness corresponding to the area A1. The laminate structure is warped such that the laminate structure is convex toward the side where the second main face is present.

摘要翻译： 多层布线基板包括层叠结构，其中树脂绝缘层和导体层交替层叠。 树脂绝缘层包括第一类树脂绝缘层和第二类树脂绝缘层，其中第二类树脂绝缘层与第一类型树脂绝缘层相比，其中含有大量的无机材料并且热膨胀系数较小。 在沿其厚度方向截取的层叠结构的横截面上，位于A2区域中的第二类树脂绝缘层的总厚度与对应于区域A2的厚度的比率大于总共 位于区域A1中的第二类型树脂绝缘层的厚度为对应于区域A1的厚度。 层压结构翘曲，使得层压结构向第二主面存在的一侧凸出。

公开(公告)号：US09006580B2

公开(公告)日：2015-04-14

申请号：US13490850

申请日：2012-06-07

申请人： Shinnosuke Maeda ,  Hajime Saiki ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Hajime Saiki ,  Satoshi Hirano

IPC分类号： H05K1/03 ,  H05K3/02 ,  H05K3/10 ,  H05K3/40 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544 ,  H01L21/683 ,  H05K1/11 ,  H05K3/46

CPC分类号： H05K3/4007 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/544 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0269 ,  H05K1/113 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09781 ,  H05K2203/072 ,  H05K2203/1105 ,  Y10T29/49155

摘要： Disclosed is a method of manufacturing a multilayer wiring substrate having a principal plane of the substrate and a rear plane thereof, having a structure such that a plurality of resin insulating layers and a plurality of conductor layers are laminated, and a plurality of chip component connecting terminals to which chip components are connectable are disposed on the principal plane of the substrate. This method has a feature including a plating layer forming process in which product plating layers which provide the plurality of chip component connecting terminals and a dummy plating layer on the surrounding of the product plating layers are formed on the surface of an exposed outermost resin insulating layer at the principal plane of the substrate. This method permits a thickness dispersion of the chip component connecting terminals to be suppressed and permits a connection reliability thereof to the chip components to be increased.

摘要翻译： 公开了一种多层布线基板的制造方法，该多层布线基板具有基板的主面及其背面，具有层叠多个树脂绝缘层和多个导体层的结构，并且多个芯片部件连接 芯片部件可连接的端子设置在基板的主平面上。 该方法具有包括镀层形成工艺的特征，其中在露出的最外层树脂绝缘层的表面上形成了在产品镀层周围形成有多个芯片部件连接端子和虚拟镀层的产品镀层 在基板的主平面上。 该方法能够抑制芯片部件连接端子的厚度分散，并且能够提高芯片部件的连接可靠性。

公开(公告)号：US08389871B2

公开(公告)日：2013-03-05

申请号：US13034792

申请日：2011-02-25

申请人： Shinnosuke Maeda ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Satoshi Hirano

IPC分类号： H05K1/11

CPC分类号： H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T29/49147

摘要： A multilayered wiring board having a stack structure multilayered by alternately stacking a plurality of conductor layers and a plurality of resin insulation layers, wherein a solder resist is provided on at least one of a first main surface side and a second main surface side of the stack structure, a plurality of openings are formed in an outermost resin insulation layer that contacts with the solder resist, a plurality of the first main surface side connecting terminals or a plurality of the second main surface side connecting terminals being made of a copper layer as a main component and positioned in a plurality of the openings, terminal outer surfaces being positioned inwardly from an outer surface of the outermost resin insulation layer, and the solder resist extends into the plurality of openings and makes contact with an outer circumference portion of each of the terminal outer surfaces.

摘要翻译： 一种多层布线基板，其具有通过交替堆叠多个导体层和多个树脂绝缘层而叠层的叠层结构，其中在所述堆叠的第一主表面侧和第二主表面侧中的至少一个上设置阻焊剂 结构中，在与阻焊剂接触的最外层树脂绝缘层中形成多个开口，多个第一主表面侧连接端子或多个第二主表面侧连接端子由铜层制成， 主要部件并且定位在多个开口中，端子外表面从最外层树脂绝缘层的外表面向内定位，并且阻焊剂延伸到多个开口中并与每个的外周部分接触 端子外表面。

公开(公告)号：US08847082B2

公开(公告)日：2014-09-30

申请号：US13109521

申请日：2011-05-17

申请人： Shinnosuke Maeda ,  Satoshi Hirano

发明人： Shinnosuke Maeda ,  Satoshi Hirano

IPC分类号： H05K1/11 ,  H05K3/46 ,  H05K3/34 ,  H05K3/24

CPC分类号： H05K1/113 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/09472

摘要： To provide a multilayer wiring substrate which can prevent migration of copper between wiring traces to thereby realize a higher degree of integration, a solder resist layer 25 having a plurality of openings 35, 36 is disposed on a top surface 31 side, and IC-chip connection terminals 41 and capacitor connection terminals 42 are buried in an outermost resin insulation layer 23 in contact with the solder resist layer 25. Each of the IC-chip connection terminals 41 and the capacitor connection terminals 42 is composed of a copper layer 44 and a plating layer 46 covering the outer surface of the copper layer 44. A conductor layer 26 present at the interface between the solder resist layer 25 and the resin insulation layer 23 is composed of a copper layer 27 and a nickel plating layer 28 covering the outer surface of the copper layer 27.

摘要翻译： 为了提供能够防止布线迹线之间的铜迁移从而实现更高的集成度的多层布线基板，具有多个开口部35,36的阻焊层25设置在顶面31侧，IC芯片 连接端子41和电容器连接端子42埋在与阻焊层25接触的最外层树脂绝缘层23中。每个IC芯片连接端子41和电容器连接端子42由铜层44和 镀覆层46覆盖铜层44的外表面。存在于阻焊层25和树脂绝缘层23之间的界面处的导体层26由铜层27和覆盖外表面的镀镍层28构成 的铜层27。