公开(公告)号：US09899308B2

公开(公告)日：2018-02-20

申请号：US15434599

申请日：2017-02-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

公开(公告)号：US09875981B2

公开(公告)日：2018-01-23

申请号：US15297452

申请日：2016-10-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Yi-Che Lai ,  Shih-Kuang Chiu

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/1401 ,  H01L2224/1412 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.

公开(公告)号：US09812340B2

公开(公告)日：2017-11-07

申请号：US15074110

申请日：2016-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

公开(公告)号：US09659806B2

公开(公告)日：2017-05-23

申请号：US14810523

申请日：2015-07-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227

Abstract: A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.

公开(公告)号：US20170040277A1

公开(公告)日：2017-02-09

申请号：US15297452

申请日：2016-10-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Yi-Che Lai ,  Shih-Kuang Chiu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/1401 ,  H01L2224/1412 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.

Abstract translation: 提供一种半导体器件，包括：具有相对的第一和第二表面的衬底和穿过第一和第二表面的多个导电通孔; 绝缘层，形成在所述基板的所述第一表面上，并暴露所述导电通孔的端部; 以及在导电通孔的端部的周边形成在绝缘层上的缓冲层，从而提高产品的可靠性和良好的产率。

公开(公告)号：US09324585B2

公开(公告)日：2016-04-26

申请号：US13654754

申请日：2012-10-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。

公开(公告)号：US20160079136A1

公开(公告)日：2016-03-17

申请号：US14823341

申请日：2015-08-11

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L23/31 ,  H01L21/52 ,  H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L21/52 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2924/18162 ,  H01L2924/3511

Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.

Abstract translation: 提供一种包装结构，其包括：具有贯穿其中的空腔的框架; 接收在所述框架的空腔中的半导体芯片，其中所述半导体芯片具有从所述框架的空腔暴露的相对的有源和非活性表面; 在所述空腔中形成的电介质层，以接触和固定所述半导体芯片的位置，其中所述电介质层的表面与所述半导体芯片的有源表面所面对的所述框架的第一表面齐平; 以及形成在电介质层的表面上的电路结构，与框架的第一表面齐平并且电连接到半导体芯片的有源表面，从而节省制造成本并减小封装结构的厚度。

公开(公告)号：US20160071784A1

公开(公告)日：2016-03-10

申请号：US14810523

申请日：2015-07-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227

Abstract: A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 半导体封装包括基极层，多个导电柱，半导体元件和封装。 基层具有相对的第一和第二表面和接收部分。 导电柱形成在第二表面上。 每个导电柱具有第一和第二端子，并且第二端子远离基底层的第二表面。 半导体元件被容纳在接收部分中，并且具有相对的有源和无源表面，并且有源表面从第一表面露出。 封装形成在第二表面上，封装导电柱和半导体元件，并且具有相对的第三和第四表面，并且导电柱的第二端子从第四表面露出。 半导体封装设置有具有细间距的导电柱。

公开(公告)号：US20140154842A1

公开(公告)日：2014-06-05

申请号：US14174988

申请日：2014-02-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L21/56 ,  H01L21/78 ,  H01L21/673 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/673 ,  H01L21/67333 ,  H01L21/67763 ,  H01L21/68 ,  H01L21/683 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract translation: 半导体封装的制造方法包括以下步骤：提供在其表面上形成有凹部和释放层的载体; 在凹部中的脱模层上设置芯片; 在芯片和释放层上形成密封剂; 去除释放层和载体; 并在密封剂和芯片上形成电路结构。 凹部的设计有助于芯片对准以防止其移位，从而提高产品的可靠性。 还提供了通过制造方法制造的半导体封装。

公开(公告)号：US09520304B2

公开(公告)日：2016-12-13

申请号：US14074148

申请日：2013-11-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Shih-Kuang Chiu

IPC: H01L23/28 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供具有载体的半导体结构，形成在载体上的电路部分和设置在电路部分上的多个半导体元件; 在所述半导体元件上设置层压部件; 在用于封装半导体元件的电路部分上形成绝缘层; 并移除载体。 层叠构件增加相邻半导体元件之间的强度，以克服当移除载体时由半导体元件和绝缘层之间的CTE失配引起的常规裂纹问题。