公开(公告)号：US11639962B1

公开(公告)日：2023-05-02

申请号：US17199874

申请日：2021-03-12

Applicant: Xilinx, Inc.

Inventor： Niravkumar Patel ,  Amitava Majumdar ,  Partho Tapan Chaudhuri

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/27

Abstract: An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.

公开(公告)号：US10110234B1

公开(公告)日：2018-10-23

申请号：US15654506

申请日：2017-07-19

Applicant: Xilinx, Inc.

Inventor： Uma E. Durairajan ,  Subodh Kumar ,  Adam Elkins ,  Ghazaleh Mirjafari ,  Amitava Majumdar

IPC: H03K19/177 ,  G01R31/3185

Abstract: Methods and apparatus are described for providing and operating an efficient infrastructure to implement a built-in clock stop and scan dump (CSSD) scheme for fabric blocks, such as block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic elements (CLEs), and the like. This is a very useful feature for system debug and can also be applied for emulation use cases (e.g., FPGA emulation). This scheme can be applied to any tiled architecture that has highly repetitive blocks. The infrastructure may include a DFx controller shared across multiple tiled blocks with some distributed logic in each block, in an effort to minimize or at least reduce area overhead. The infrastructure may also minimize or at least reduce utilization of fabric resources in an effort to ensure the least perturbation of the original design, such that the design issues being debugged can be easily reproduced.

公开(公告)号：US09798352B1

公开(公告)日：2017-10-24

申请号：US14939704

申请日：2015-11-12

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Balakrishna Jayadev

IPC: G01R31/317 ,  G01R31/3185 ,  G06F1/10

CPC classification number: G06F1/10 ,  G01R31/31704 ,  G01R31/31705 ,  G01R31/31726 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318583

Abstract: A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input signal at a scan input and to receive a first clock signal in a first clock domain at a clock input; a storage element having a data input configured to receive an output of the first dual-edge storage circuit; a second dual-edge storage circuit configured to receive an output of the storage element at a scan input and to receive a second clock signal in a second clock domain at a clock input; and a pulse generator configured to provide, to a clock input of the storage element, a pulse signal having a pulse width selected to enable the second dual-edge storage element to store the output of the first dual-edge storage element.

公开(公告)号：US09761533B2

公开(公告)日：2017-09-12

申请号：US14885757

申请日：2015-10-16

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Amitava Majumdar ,  Glenn O'Rourke ,  Inderjit Singh

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/152 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/78 ,  H01L2221/68304 ,  H01L2224/81 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/11 ,  H01L2221/68381 ,  H01L22/00 ,  H01L2224/1181

Abstract: Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

公开(公告)号：US08884804B1

公开(公告)日：2014-11-11

申请号：US14089222

申请日：2013-11-25

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Siva Charan Nimmagadda ,  Baanurathan Sadasivam ,  Richard W. Swanson ,  Yohan Frans

IPC: H03M1/50 ,  H03M1/12 ,  H03L7/081 ,  H03L7/087 ,  H03L7/089 ,  H03M1/00

CPC classification number: G04F10/005 ,  H03L7/00 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0895 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233

Abstract: An apparatus relating generally to time-to-digital conversion is disclosed. In this apparatus, a time-to-digital converter is coupled to a period sensor. The period sensor includes a pulse generator to generate a pulse. An integrator of the period sensor is coupled to receive the pulse to generate an analog voltage signal responsive to the pulse. The time-to-digital converter includes an analog-to-digital converter coupled to provide a digital signal associated with the analog voltage signal.

Abstract translation: 公开了一种与时间 - 数字转换相关的装置。 在该装置中，时间 - 数字转换器耦合到周期传感器。 周期传感器包括产生脉冲的脉冲发生器。 耦合周期传感器的积分器以接收脉冲以产生响应脉冲的模拟电压信号。 时间 - 数字转换器包括耦合以提供与模拟电压信号相关联的数字信号的模拟 - 数字转换器。

公开(公告)号：US11755804B2

公开(公告)日：2023-09-12

申请号：US17646184

申请日：2021-12-28

Applicant: Xilinx, Inc.

Inventor： Albert Shih-Huai Lin ,  Rambabu Nerukonda ,  Niravkumar Patel ,  Amitava Majumdar

IPC: G06F30/333 ,  G06F30/367 ,  G06F30/396 ,  G06F30/398 ,  G06F30/20 ,  G06F11/267 ,  G06F11/27 ,  H01L25/00 ,  H03K19/17732 ,  H03K19/17764 ,  G06F115/08 ,  H01L21/66

CPC classification number: G06F30/333 ,  H03K19/17732 ,  H03K19/17764 ,  G06F11/267 ,  G06F11/27 ,  G06F30/20 ,  G06F30/367 ,  G06F30/396 ,  G06F30/398 ,  G06F2115/08 ,  H01L22/34 ,  H01L25/00

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

公开(公告)号：US20230205959A1

公开(公告)日：2023-06-29

申请号：US17646184

申请日：2021-12-28

Applicant: Xilinx, Inc.

Inventor： Albert Shih-Huai Lin ,  Rambabu Nerukonda ,  Niravkumar Patel ,  Amitava Majumdar

IPC: G06F30/333

CPC classification number: G06F30/333 ,  G06F2115/08

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

公开(公告)号：US10754759B1

公开(公告)日：2020-08-25

申请号：US15889001

申请日：2018-02-05

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Georgios Tzimpragos ,  Jason Villarreal ,  Kumar Deepak ,  Jayashree Rangarajan

IPC: G06F11/00 ,  G06F11/36

Abstract: An execution circuit inputs a plurality of data units, performs unit operations on the data units, and registers results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation of the unit operations, and outputs a start signal to the execution circuit to activate each unit operation and/or a completion signal to indicate completion of each unit operation. A debug circuit stores breakpoint flags associated with the unit operations. Each breakpoint flag has a state that specifies whether to stop oscillations of the clock signal. The debug circuit further receives the start and/or completion signal and evaluates, while the clock signal oscillates to the execution circuit, a state of the start and/or completion signal and a state of the breakpoint flag associated with the unit operation. Oscillations of the clock signal are stopped in response to the evaluation of the signals.

公开(公告)号：US09989572B1

公开(公告)日：2018-06-05

申请号：US14494400

申请日：2014-09-23

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Ganesh Hariharan ,  Amitava Majumdar

IPC: G01R31/02 ,  G01R31/28 ,  G01R1/067

CPC classification number: G01R31/021 ,  G01R1/067 ,  G01R31/28

Abstract: A method and a probe device for testing an interposer prior to assembly are described herein. The method includes coupling a plurality of probe tips of a probe device to the plurality of signal interconnect paths of the interposer to be tested. A test signal is provided from the probe device to the plurality of signal interconnect paths of the interposer and a quality characteristic of signal interconnect paths of the interposer is detected based on behavior of the interposer in response to the test signal.

公开(公告)号：US11263377B1

公开(公告)日：2022-03-01

申请号：US17219174

申请日：2021-03-31

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Albert Shih-Huai Lin ,  Partho Tapan Chaudhuri ,  Niravkumar Patel

IPC: G06F30/333 ,  G06F30/3308 ,  G06F30/398 ,  G06F11/00 ,  G01R31/28 ,  H01L25/00 ,  H03K19/00 ,  G06F115/08 ,  G06F11/08

Abstract: A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.