公开(公告)号：US11355412B2

公开(公告)日：2022-06-07

申请号：US16147286

申请日：2018-09-28

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Gamal Refai-Ahmed ,  Henley Liu ,  Myongseob Kim ,  Tien-Yu Lee ,  Suresh Ramalingam ,  Cheang-Whang Chang

IPC: H01L23/367 ,  H01L23/427 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/07

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

公开(公告)号：US11330738B1

公开(公告)日：2022-05-10

申请号：US17133525

申请日：2020-12-23

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Huayan Wang ,  Suresh Ramalingam ,  Volker Aue

IPC: H05K7/20 ,  H05K1/02 ,  H01Q1/00

Abstract: An electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.

公开(公告)号：US11315858B1

公开(公告)日：2022-04-26

申请号：US16903376

申请日：2020-06-17

Applicant: XILINX, INC.

Inventor： Yu Hsiang Sun ,  Suresh Ramalingam ,  Tien-Yu Lee ,  Jaspreet Singh Gandhi

IPC: H01L23/498 ,  H01L23/00

Abstract: A chip package assembly having robust solder connections are described herein. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die and a package substrate. Solder pads are arranged to connect to pillars of the IC die via solder connections. Solder resist in the corners of the package substrate and surrounding the solder connections may be inhibited from cracking isolating the portion of the solder resist surrounding the solder pads and/or by providing an offset between centerlines of the pillars and solder pads.

公开(公告)号：US11282775B1

公开(公告)日：2022-03-22

申请号：US16942930

申请日：2020-07-30

Applicant: XILINX, INC.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam

IPC: H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L23/28 ,  H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L21/768 ,  H01L21/683 ,  H01L23/31

Abstract: A chip package assembly having pillars extending between an interconnect layer and solder balls, and methods for manufacturing the same are provide. The pillars decouple stress from the interconnect layer, making crack initiation and propagation to the interconnect layer less likely, resulting in a more robust assembly. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die, an interconnect layer and a plurality of pillars. The IC dies includes a die body containing functional circuitry. The body has a lower surface, an upper surface and sides. The IC die includes contact pads coupled to the functional circuitry and exposed on the lower surface of the die body. The interconnect layer is formed on the lower surface of the body. The plurality of pillars are formed on the interconnect layer and electrically couple to the contact pads through routing formed through the interconnect layer.

公开(公告)号：US11043484B1

公开(公告)日：2021-06-22

申请号：US16362134

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  James Karp ,  Siow Chek Tan ,  Martin L. Voogel ,  Mohsen H. Mardi ,  Suresh Ramalingam ,  David M. Mahoney

IPC: H01L27/02 ,  G01R1/04 ,  H01L25/065 ,  H01L23/498

Abstract: Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

公开(公告)号：US20200006186A1

公开(公告)日：2020-01-02

申请号：US16024670

申请日：2018-06-29

Applicant: Xilinx, Inc.

Inventor： Hong-Tsz Pan ,  Jonathan Chang ,  Nui Chong ,  Henley Liu ,  Gamal Refai-Ahmed ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/528

Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.

公开(公告)号：US20190318975A1

公开(公告)日：2019-10-17

申请号：US15951941

申请日：2018-04-12

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Suresh Ramalingam ,  Siow Chek Tan ,  Gamal Refai-Ahmed

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

公开(公告)号：US09418966B1

公开(公告)日：2016-08-16

申请号：US14665908

申请日：2015-03-23

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/535 ,  H01L23/528 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/01 ,  H01L24/11 ,  H01L24/81 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/16145 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: In one example, a semiconductor assembly comprises a first IC die, a second IC die, and a bridge module. The first IC die includes, on a top side thereof, first interconnects of a plurality of interconnects and first inter-die contacts of a plurality of inter-die contacts. The second IC die includes, on a top side thereof, second interconnects of the plurality of interconnects and second inter-die contacts of the plurality of inter-die contracts. The bridge module is disposed between the first interconnects and the second interconnects and includes bridge interconnects on a top side thereof, the bridge interconnects mechanically and electrically coupled to the plurality of inter-die contacts, and layer(s) of conductive interconnect disposed on the top side thereof to route signals between the first IC and the second IC. A back side of the bridge module does not extend beyond a height of the plurality of interconnects.

Abstract translation: 在一个示例中，半导体组件包括第一IC管芯，第二IC管芯和桥接模块。 第一IC芯片在其顶侧上包括多个互连的第一互连和多个晶片间接触的第一晶片间接触。 第二IC管芯在其顶侧上包括多个互连件中的第二互连和多个管芯间合同的第二管芯间接触。 桥模块设置在第一互连和第二互连之间，并且在其顶侧上包括桥互连，桥互连机械地和电耦合到多个管芯间接触，以及设置在第二互连层上的导电互连层 其顶侧以在第一IC和第二IC之间路由信号。 桥模块的背面不延伸超出多个互连的高度。

公开(公告)号：US20140262440A1

公开(公告)日：2014-09-18

申请号：US13827048

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Namhoon Kim ,  Joong-Ho Kim ,  Suresh Ramalingam ,  Paul Y. Wu ,  Woon-Seong Kwon ,  Dennis C.P. Leung

IPC: H05K1/02

CPC classification number: H05K1/02 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/16225

Abstract: A multi-layer core organic package substrate includes: a multi-layer core comprising at least two organic core layers, wherein two of the at least two organic core layers are separated by a core metal layer; a first plurality of build-up layers formed on top of the multi-core layer; and a second plurality of build-up layers formed below the multi-core layer.

Abstract translation: 多层核心有机封装基板包括：包含至少两个有机芯层的多层芯，其中所述至少两个有机芯层中的两个被芯金属层分隔开; 形成在所述多芯层的顶部上的第一多个堆积层; 以及形成在所述多芯层下方的第二多个积聚层。

公开(公告)号：US12136613B2

公开(公告)日：2024-11-05

申请号：US17669252

申请日：2022-02-10

Applicant: XILINX, INC.

Inventor： Li-Sheng Weng ,  Suresh Ramalingam ,  Hong Shi

IPC: H01L23/00 ,  H01L25/16

Abstract: A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.