公开(公告)号：US12062853B2

公开(公告)日：2024-08-13

申请号：US18313727

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghyun Baek ,  Seungtae Ko ,  Kijoon Kim ,  Juho Son ,  Sangho Lee ,  Youngju Lee ,  Jungyub Lee ,  Yonghun Cheon ,  Dohyuk Ha

IPC: H01Q21/06 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q1/42 ,  H04B7/0413 ,  H05K1/18 ,  H05K9/00

CPC classification number: H01Q21/065 ,  H01Q1/2283 ,  H01Q1/246 ,  H01Q1/42 ,  H04B7/0413 ,  H05K1/181 ,  H05K9/0049 ,  H05K2201/042 ,  H05K2201/10015 ,  H05K2201/10098 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. According to the disclosure, an antenna module includes a first substrate layer on which at least one substrate is stacked; an antenna coupled to an upper end surface of the first substrate layer; a second substrate layer having an upper end surface coupled to a lower end surface of the first substrate layer and on which at least one substrate is stacked; and a radio frequency (RF) element coupled to a lower end surface of the second substrate layer.

公开(公告)号：US11682845B2

公开(公告)日：2023-06-20

申请号：US17373000

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghyun Baek ,  Seungtae Ko ,  Kijoon Kim ,  Juho Son ,  Sangho Lee ,  Youngju Lee ,  Jungyub Lee ,  Yonghun Cheon ,  Dohyuk Ha

IPC: H01Q21/06 ,  H01Q1/24 ,  H01Q1/42 ,  H05K1/18 ,  H05K9/00 ,  H04B7/0413

CPC classification number: H01Q21/065 ,  H01Q1/246 ,  H01Q1/42 ,  H04B7/0413 ,  H05K1/181 ,  H05K9/0049 ,  H05K2201/042 ,  H05K2201/10015 ,  H05K2201/10098 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. According to the disclosure, an antenna module includes a first substrate layer on which at least one substrate is stacked; an antenna coupled to an upper end surface of the first substrate layer; a second substrate layer having an upper end surface coupled to a lower end surface of the first substrate layer and on which at least one substrate is stacked; and a radio frequency (RF) element coupled to a lower end surface of the second substrate layer.

公开(公告)号：US20180323708A1

公开(公告)日：2018-11-08

申请号：US15772487

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： William J. LAMBERT ,  Mathew MANUSHAROW

IPC: H02M3/155

CPC classification number: H02M3/155 ,  H01L25/10 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10159 ,  H05K2201/10166 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2201/10719

Abstract: A printed circuit board (PCB) includes one or more voltage rails and an integrated voltage regulator (IVR) electrically coupled to supply current to a voltage rail. The PCB also includes a PCB current source electrically coupled to supply a supplementary current to the voltage rail.

公开(公告)号：US20180270957A1

公开(公告)日：2018-09-20

申请号：US15459787

申请日：2017-03-15

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan ,  Ram S. Viswanath

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/00 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/183 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/141 ,  H05K3/0014 ,  H05K3/303 ,  H05K3/46 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/10628 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: Embodiments of the present disclosure provide techniques for a printed circuit board (PCB) with a recess to accommodate discrete components of a package attachable to the PCB, in accordance with some embodiments. In one embodiment, a PCB may include a recess disposed in at least a portion of the PCB, to receive at least a portion of a package. The package may be attachable to the PCB via a plurality of connectors. The connectors may be disposed on a side of the package that faces the PCB. The portion of the package may include one or more discrete components disposed on the side of the package that faces the PCB. The recess may have a depth to accommodate those discrete components that have a height that is greater than a height of the connectors. Other embodiments may be described and/or claimed.

公开(公告)号：US20180192519A1

公开(公告)日：2018-07-05

申请号：US15855808

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： Fay HUA ,  Hong XIE ,  Gregorio R. MURTAGIAN ,  Amit ABRAHAM ,  Alan C. MCALLISTER ,  Ting ZHONG

IPC: H05K1/18 ,  H01R12/52 ,  H05K3/34 ,  H01L23/498 ,  H05K3/40 ,  H01R33/76

CPC classification number: H05K1/181 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/00 ,  H01R12/52 ,  H01R33/7607 ,  H05K3/3421 ,  H05K3/4007 ,  H05K2201/10719

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.

公开(公告)号：US09927833B2

公开(公告)日：2018-03-27

申请号：US14907117

申请日：2013-07-22

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： John Norton

IPC: G06F1/16 ,  H05K1/18 ,  H05K3/30 ,  H05K3/10 ,  H05K3/40

CPC classification number: G06F1/16 ,  H05K1/18 ,  H05K3/103 ,  H05K3/30 ,  H05K3/4046 ,  H05K2201/09063 ,  H05K2201/10287 ,  H05K2201/10719 ,  H05K2201/10962

Abstract: A printed circuit board (PCB) can include a central processing unit (CPU) installed on a first surface of the PCB. The PCB can also include a cable routed on a second surface of the PCB parallel to the first surface. The PCB can further include a hole extending through a thickness of the PCB to connect the first surface and the second surface. The cable can extend through the hole to be coupled to the CPU.

公开(公告)号：US20180084634A1

公开(公告)日：2018-03-22

申请号：US15271525

申请日：2016-09-21

Applicant: Seagate Technology LLC

Inventor： David Michael Davis ,  Gary Edward Webb

IPC: H05K1/02 ,  H05K3/34 ,  H05K1/18

CPC classification number: H05K1/029 ,  H01L23/50 ,  H05K1/0243 ,  H05K1/0245 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10212 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: A printed circuit board assembly includes a printed circuit board having a plurality of signal lanes. The PCBA also includes at least one application-specific integrated circuit operatively mounted to the printed circuit board and connected with the plurality of signal lanes. The PCBA includes a first configuration element operatively mounted to the printed circuit board in a first orientation and at a first location and having a first bridging element for providing an electrical connection between at least a first pair of signal lanes selected from the plurality of signal lanes. The first configuration element also includes a second bridging element so that if the first configuration element were operatively mounted to the printed circuit board in a different, second orientation relative to the printed circuit board, the second bridging element would provide an electrical connection between at least a second pair of signal lanes.

公开(公告)号：US20180047660A1

公开(公告)日：2018-02-15

申请号：US15233906

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  David Francis BERDY ,  Daeik Daniel KIM ,  Jonghae KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49805 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L24/02 ,  H05K1/0218 ,  H05K3/3436 ,  H05K2201/10719

Abstract: A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.

公开(公告)号：US09860973B2

公开(公告)日：2018-01-02

申请号：US15220575

申请日：2016-07-27

Applicant: FUJITSU LIMITED

Inventor： Yoshihiro Morita

IPC: H05K1/02

CPC classification number: H05K1/0243 ,  H05K2201/10325 ,  H05K2201/10356 ,  H05K2201/10719

Abstract: A contactor coupled to an electrode of a semiconductor package mounted on a mounting surface of a wiring board, the contactor includes: a cable including a core line; a connector attached to a front end of the cable, and to be inserted into a through hole that penetrates the wiring board in a thickness direction thereof; and a signal land formed on a front end surface of the connector, and electrically coupled with the core line.

公开(公告)号：US20170367180A1

公开(公告)日：2017-12-21

申请号：US15184662

申请日：2016-06-16

Applicant: ALCATEL-LUCENT CANADA INC.

Inventor： James M. SCHRIEL ,  Alex L. CHAN ,  Paul J. BROWN

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/18

CPC classification number: H05K1/0296 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181 ,  H05K3/0005 ,  H05K2201/10704 ,  H05K2201/10712 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.