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公开(公告)号：US20180026529A1
公开(公告)日：2018-01-25
申请号：US15674026
申请日：2017-08-10
Inventor： Peter Vlasenko , Huy Tuong Mai
CPC classification number: H02M3/07 , G05F1/625 , G05F3/02 , H02M1/34 , H02M3/073 , H03K5/086 , H03L7/0895
Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
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公开(公告)号：US20170322730A1
公开(公告)日：2017-11-09
申请号：US15655336
申请日：2017-07-20
Inventor： Peter B. GILLINGHAM , Graham ALLAN
IPC: G06F3/06 , G11C16/32 , G11C16/28 , G11C16/10 , G11C7/22 , G11C7/10 , G06F13/16 , G11C14/00 , G11C16/04 , H03K5/00
CPC classification number: G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
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公开(公告)号：US09806925B2
公开(公告)日：2017-10-31
申请号：US15007303
申请日：2016-01-27
Inventor： D.J. Richard Van Nee
CPC classification number: H04L27/2602 , H04L1/0002 , H04L5/1446 , H04L25/08 , H04L27/2605 , H04L27/2607 , H04L27/2647 , H04L27/2662
Abstract: An OFDM system uses a normal mode which has a symbol length T, a guard time TG and a set of N sub-carriers, which are orthogonal over the time T, and one or more fallback modes which have symbol lengths KT and guard times KTG where K is an integer greater than unity. The same set of N sub-carriers is used for the fallback modes as for the normal mode. Since the same set of sub-carriers is used, the overall bandwidth is substantially constant, so alias filtering does not need to be adaptive. The Fourier transform operations are the same as for the normal mode. Thus fallback modes are provided with little hardware cost. In the fallback modes the increased guard time provides better delay spread tolerance and the increased symbol length provides improved signal to noise performance, and thus increased range, at the cost of reduced data rate.
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公开(公告)号：US20170288649A1
公开(公告)日：2017-10-05
申请号：US15490557
申请日：2017-04-18
Inventor： Barry Alan HOBERMAN , Daniel L. HILLMAN , Jon Shiell
CPC classification number: H03K3/012 , G06F1/3203 , G06F1/324 , G06F1/3296 , H01L2924/00 , H01L2924/0002 , H02J4/00 , Y02D10/126 , Y02D10/172 , Y02D50/20 , Y10T307/406 , Y10T307/414
Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.
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公开(公告)号：US09780073B2
公开(公告)日：2017-10-03
申请号：US14886190
申请日：2015-10-19
Inventor： Peter B. Gillingham
IPC: H05K1/11 , H01L25/065 , G11C5/02 , G11C5/06 , H01L23/48 , H01L23/544 , H01L21/02 , H01L21/82 , H03K17/00 , H01L23/528 , H01L23/00
CPC classification number: H01L25/0657 , G11C5/02 , G11C5/06 , H01L21/02697 , H01L21/82 , H01L23/481 , H01L23/5286 , H01L23/544 , H01L24/03 , H01L24/16 , H01L2223/54433 , H01L2223/5444 , H01L2224/0401 , H01L2224/06181 , H01L2225/06513 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06548 , H01L2225/06562 , H01L2924/01055 , H01L2924/01078 , H01L2924/14 , H03K17/00 , H01L2924/00
Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.
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Patent Agency Ranking
公开(公告)号：US20170272085A1
公开(公告)日：2017-09-21
申请号：US15479691
申请日：2017-04-05
Inventor： Peter Vlasenko , Dieter Haerle
CPC classification number: H03L7/081 , H03L7/0814 , H03L7/0818 , H03L7/0891 , H03L7/095 , H03L7/10
Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.
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公开(公告)号：US09767881B2
公开(公告)日：2017-09-19
申请号：US15054873
申请日：2016-02-26
Inventor： Jin-Ki Kim , HakJune Oh
IPC: G11C7/00 , G11C11/406
CPC classification number: G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
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公开(公告)号：USRE46549E1
公开(公告)日：2017-09-12
申请号：US14025203
申请日：2013-09-12
Inventor： Eun-Young Minn , Young-Hoon Park , Chi-Hoon Lee , Hyo-Dong Ban
IPC: H01L23/544 , H01L23/26 , H01L23/31
CPC classification number: H01L23/26 , H01L23/3178 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
Abstract: An integrated circuit chip having an anti-moisture-absorption film at the edge thereof and a method of forming the anti-moisture-absorption film are provided. In the integrated circuit chip which has predetermined devices inside and whose uppermost layer is covered with a passivation film, a trench is formed by etching interlayer dielectric films to a predetermined depth along the perimeter of the integrated circuit chip to be adjacent to the edge of the integrated circuit chip and an anti-moisture-absorption film is formed to fill the trench or is formed on the sidewall of the trench to a predetermined thickness, in order to prevent moisture from seeping into the edge of the integrated circuit chip. Moisture is effectively prevented from seeping into the edge of the chip by forming the anti-moisture-absorption film at the edge of the chip using the conventional processes of manufacturing the integrated circuit chip without an additional process.
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公开(公告)号：US20170229188A1
公开(公告)日：2017-08-10
申请号：US15411138
申请日：2017-01-20
Inventor： Jin-Ki KIM
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11524
Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
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公开(公告)号：US09660616B2
公开(公告)日：2017-05-23
申请号：US14865905
申请日：2015-09-25
Inventor： Barry Alan Hoberman , Daniel L Hillman , Jon Shiell
CPC classification number: H03K3/012 , G06F1/3203 , G06F1/324 , G06F1/3296 , H01L2924/00 , H01L2924/0002 , H02J4/00 , Y02D10/126 , Y02D10/172 , Y02D50/20 , Y10T307/406 , Y10T307/414
Abstract: Systems and methods for managing power in an integrated circuit using power islands are disclosed. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.
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