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    Isolated electrostatic wafer blade clamp
    91.
    发明授权
    Isolated electrostatic wafer blade clamp 失效
    隔离静电晶片刀片夹

    公开(公告)号：US4962441A

    公开(公告)日：1990-10-09

    申请号：US335556

    申请日：1989-04-10

    Applicant: Kenneth S. Collins

    Inventor： Kenneth S. Collins

    IPC: B65H3/18 ,  B65H5/00 ,  H01L21/677 ,  H01L21/683 ,  H01L21/687 ,  H02N13/00

    CPC classification number: H01L21/67748 ,  H01L21/6831 ,  H01L21/68707

    Abstract: An electrostatic-clamping robotic-type semiconductor wafer-holding blade designed to optimize the electrostatic clamping force and decrease the required clamping voltage. The wafer blade includes: a base; interleaved electrodes formed on the base, alternating electrodes being connected in common electrically; and preferably a layer of dielectric material such as Al.sub.2 O.sub.3 having a thickness ranging between 2 mils and 15 mils disposed over the interleaved electrodes and the base to minimize the applied voltage necessary to flatten the wafer against the blade, without dielectric breakdown. The ratio of electrode width to the distance between electrodes ranges from 3/1 to 2/1 to optimize the electrostatic clamping force exerted by the blade.

    Process for PECVD of silicon oxide using TEOS decomposition
    92.
    发明授权
    Process for PECVD of silicon oxide using TEOS decomposition 失效

    公开(公告)号：US4892753A

    公开(公告)日：1990-01-09

    申请号：US262993

    申请日：1988-10-26

    Applicant: David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    Inventor： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC: C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/509 ,  C23C16/54 ,  H01L21/314 ,  H01L21/316

    CPC classification number: C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    CVD of silicon oxide using TEOS decomposition and in-situ planarization process
    93.
    发明授权
    CVD of silicon oxide using TEOS decomposition and in-situ planarization process 失效
    使用TEOS分解和原位平面化处理的氧化硅CVD

    公开(公告)号：US4872947A

    公开(公告)日：1989-10-10

    申请号：US262992

    申请日：1988-10-26

    Applicant: David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    Inventor： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC: C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/509 ,  C23C16/54 ,  H01L21/314 ,  H01L21/316

    CPC classification number: C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either along or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    Abstract translation: 公开了一种高压，高通量，单晶片，半导体处理反应器，其能够通过溅射单独地或作为一部分的溅射进行热CVD，等离子体增强CVD，等离子体辅助回蚀，等离子体自清洁和沉积形貌修饰 原位多步处理。 还公开了用于形成高度保形二氧化硅层的低温CVD工艺。 该过程使用非常高的室压和低温，以及TEOS和臭氧反应物。 低温CVD二氧化硅沉积步骤特别可用于平坦化下面的阶梯介电层，或者沿着或结合随后的各向同性蚀刻。 用于形成平坦化的二氧化硅层的优选的原位多步骤方法使用（1）在低温和高压下高速二氧化硅沉积，随后（2）也在高压下沉积保形二氧化硅层，以及 低温，随后（3）高速各向同性蚀刻，优选在低温和高压下，在用于两个氧化物沉积步骤的相同反应器中。 公开了用于不同应用的步骤的各种组合，优选的反应器自清洁步骤也是如此。

    Method of producing a plasma-resistant thermal oxide coating
    98.
    发明授权
    Method of producing a plasma-resistant thermal oxide coating 有权
    制造耐等离子体热氧化物涂层的方法

    公开(公告)号：US08758858B2

    公开(公告)日：2014-06-24

    申请号：US13374980

    申请日：2012-01-25

    Applicant: Jennifer Y. Sun ,  Li Xu ,  Kenneth S. Collins ,  Thomas Graves ,  Ren-Guan Duan ,  Senh Thach

    Inventor： Jennifer Y. Sun ,  Li Xu ,  Kenneth S. Collins ,  Thomas Graves ,  Ren-Guan Duan ,  Senh Thach

    IPC: B05D3/02

    CPC classification number: C23C16/4404 ,  H01J37/32467 ,  H01J37/32477

    Abstract: A method of creating a plasma-resistant thermal oxide coating on a surface of an article, where the article is comprised of a metal or metal alloy which is typically selected from the group consisting of yttrium, neodymium, samarium, terbium, dysprosium, erbium, ytterbium, scandium, hafnium, niobium or combinations thereof. The oxide coating is formed using a time-temperature profile which includes an initial rapid heating rage, followed by a gradual decrease in heating rate, to produce an oxide coating structure which is columnar in nature. The grain size of the crystals which make up the oxide coating is larger at the surface of the oxide coating than at the interface between the oxide coating and the metal or metal alloy substrate, and the oxide coating is in compression at the interface between the oxide coating and the metal or metal alloy substrate.

    Abstract translation: 一种在制品的表面上产生耐等离子体热氧化物涂层的方法，其中制品由金属或金属合金组成，金属或金属合金通常选自钇，钕，钐，铽，镝，铒， 镱，钪，铪，铌或其组合。 使用时间 - 温度曲线形成氧化物涂层，其包括初始的快速加热，然后逐渐降低加热速率，以产生本质上为柱状的氧化物涂层结构。 构成氧化物涂层的晶体的晶粒尺寸在氧化物涂层的表面比在氧化物涂层和金属或金属合金衬底之间的界面处大，并且氧化物涂层在氧化物之间的界面处被压缩 涂层和金属或金属合金基材。

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