公开(公告)号：US20160094362A1

公开(公告)日：2016-03-31

申请号：US14835549

申请日：2015-08-25

Applicant: Linear Technology Corporation

Inventor： Ciaran Brennan

IPC: H04L12/40 ,  H03K17/687 ,  H04L12/12 ,  H03K3/012

CPC classification number: H04L12/40039 ,  H03K3/012 ,  H03K17/164 ,  H03K17/687 ,  H04L12/12 ,  H04L12/40032 ,  H04L2012/40215

Abstract: A Controller Area Network (CAN) driver (a transmitter) includes a conventional main driver having an open drain first driver MOSFET, for pulling up a first conductor of a bus in a dominant state, and an open drain second driver MOSFET, for pulling down a second conductor of the bus in the dominant state. Since it is difficult to perfectly match the driver MOSFET characteristics for conducting exactly equal currents during turning on and turning off, significant common mode fluctuations occur, resulting in electromagnetic emissions. Source followers are respectively connected in parallel with the first driver MOSFET and the second driver MOSFET for creating a low common mode loading impedance on the conductors during times when the main driver MOSFETs are turning on and turning off to greatly reduce any common mode fluctuations caused by the main driver MOSFETs.

Abstract translation: 控制器局域网（CAN）驱动器（发射机）包括具有开漏第一驱动器MOSFET的常规主驱动器，用于提升处于主导状态的总线的第一导体和用于下拉的开漏第二驱动器MOSFET 总统的第二个导体处于主导地位。 由于在导通和关断期间难以完全匹配驱动器MOSFET特性以进行完全相等的电流，因此会产生显着的共模波动，导致电磁辐射。 源极跟随器分别与第一驱动器MOSFET和第二驱动器MOSFET并联连接，用于在主驱动器MOSFET导通和关断的时间在导体上产生低共模负载阻抗，以大大减少由 主要驱动MOSFET。

公开(公告)号：US20160054777A1

公开(公告)日：2016-02-25

申请号：US14831632

申请日：2015-08-20

Applicant: Linear Technology Corporation

Inventor： David Dwelley ,  Andrew J. Gardner

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/40 ,  G06F1/26

CPC classification number: G06F1/3206 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/4022 ,  G06F13/4282 ,  H04L12/10 ,  H04L12/40045

Abstract: A PoDL system includes a PSE supplying DC power and Ethernet data over a single twisted wire pair to a PD. Prior to coupling the DC voltage source to the wire pair, the PD needs to receive sufficient power to perform a detection and classification routine with the PSE to determine whether the PD is PoDL-compatible. The PSE has a low current, pull-up current source coupled to a first wire in the wire pair via a first inductor. This pull-up current charges a capacitor in the PD to a desired operating voltage, and the operating voltage is used to power a PD logic circuit. The PD logic circuit and a PSE logic circuit then control pull-down transistors to communicate detection and classification data via the first wire. After the handshaking phase, the PSE then applies the DC voltage source across the wire pair to power the PD for normal operation.

Abstract translation: PoDL系统包括通过单个双绞线对PD提供直流电源和以太网数据的PSE。 在将直流电压源耦合到线对之前，PD需要接收足够的电力以执行与PSE的检测和分类例程，以确定PD是否与PoDL兼容。 PSE具有通过第一电感器耦合到线对中的第一线的低电流，上拉电流源。 该上拉电流将PD中的电容器充电到期望的工作电压，并且使用工作电压为PD逻辑电路供电。 然后，PD逻辑电路和PSE逻辑电路控制下拉晶体管，以经由第一线路传送检测和分类数据。 在握手阶段之后，PSE将通过电线对施加直流电压源，为PD供电以进行正常工作。

公开(公告)号：US20160035644A1

公开(公告)日：2016-02-04

申请号：US14630239

申请日：2015-02-24

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Edward William Olsen ,  Leonard Shtargot ,  David Roy Ng ,  Jeffrey Kingan Witt

IPC: H01L23/367 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L21/268 ,  H01L21/2855 ,  H01L21/2885 ,  H01L21/3105 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/19 ,  H01L2224/29111 ,  H01L2224/2912 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14

Abstract: An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the integrated circuit package.

Abstract translation: 集成电路封装可以包括半导体管芯，散热器和封装材料。 半导体管芯可以包含电子电路和暴露的电连接到电子电路。 散热器可以是导热的并且可以具有基本上平行于第一外表面的第一外表面和第二外表面。 第一外表面可以以导热方式固定到半导体管芯的硅侧的所有部分。 除了散热器的第二表面之外，封装材料可以是不导电的，并且可以完全封装半导体管芯和散热器。 散热器的第二表面可以是可焊接的并且可以形成集成电路封装的外表面的一部分。

公开(公告)号：US20150362936A1

公开(公告)日：2015-12-17

申请号：US14706555

申请日：2015-05-07

Applicant: Linear Technology Corporation

Inventor： Amitkumar P. Patel ,  Carl Nelson

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  H02M2001/007

Abstract: In an LDO regulator, two feedback loops are created. The first feedback loop includes a high power PNP bipolar power transistor connected in series between the input voltage Vin terminal and the output voltage Vout terminal. The first feedback loop includes a first error amplifier that controls a drive transistor to drive the base of the power transistor such that Vout matches a set voltage Vset. This first feedback loop circuitry uses an operating voltage (the upper rail voltage) that is regulated by a second feedback loop and is approximately 300 mV greater than Vout. As a result, the control circuitry will be powered by a low ripple supply to improve output PSRR. Further, the power transistor is connected such that any noise in the input voltage is a common mode voltage across the base-emitter of the transistor.

Abstract translation: 在LDO调节器中，创建了两个反馈回路。 第一反馈回路包括串联连接在输入电压Vin端和输出电压Vout端之间的高功率PNP双极功率晶体管。 第一反馈回路包括第一误差放大器，其控制驱动晶体管驱动功率晶体管的基极，使得Vout匹配设定电压Vset。 该第一反馈回路电路使用由第二反馈回路调节的工作电压（上轨电压），并且比Vout大大约300mV。 因此，控制电路将由低纹波电源供电，以改善输出PSRR。 此外，功率晶体管被连接成使得输入电压中的任何噪声都是晶体管的基极 - 发射极两端的共模电压。

公开(公告)号：US20150333935A1

公开(公告)日：2015-11-19

申请号：US14712855

申请日：2015-05-14

Applicant: Linear Technology Corporation

Inventor： Andrew J. Gardner ,  David Dwelley ,  Jeffrey L. Heath

IPC: H04L25/02 ,  H04L12/10 ,  H02M3/158

CPC classification number: H04L25/0266 ,  H02M3/156 ,  H02M3/158 ,  H02M2001/0029 ,  H04L12/10 ,  H04L25/0272

Abstract: A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and differential Ethernet data over a single twisted wire pair to a Powered Device (PD). Due to start-up perturbations, PD load current variations, and other causes, dV/dt noise is introduced in the power signal. Such noise may be misinterpreted as data unless mitigated somehow. Rather than increasing the values of the passive filtering components conventionally used for decoupling/coupling the power and data from/to the wire pair, active circuitry is provided in the PSE, PD, or both to limit dV/dt in the power signal. Such circuitry may be implemented on the same chip as the PSE controller or PD controller. Therefore, the sizes of the passive components in the decoupling/coupling networks may be reduced.

Abstract translation: 数据线电源（PoDL）系统包括通过单个双绞线对有源设备（PD）提供直流电源和差分以太网数据的电源设备（PSE）。 由于启动扰动，PD负载电流变化和其他原因，dV / dt噪声被引入功率信号。 这种噪声可能被误解为数据，除非以某种方式得到缓解。 不是增加常规用于从/对线对去耦/耦合功率和数据的无源滤波组件的值，而是在PSE，PD或两者中提供有源电路以限制功率信号中的dV / dt。 这种电路可以在与PSE控制器或PD控制器相同的芯片上实现。 因此，可以减小去耦/耦合网络中的无源组件的尺寸。

公开(公告)号：USRE45798E1

公开(公告)日：2015-11-10

申请号：US14473745

申请日：2014-08-29

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： David M. Thomas ,  Alfio Zanchi

IPC: H03M1/20 ,  H04B17/10

CPC classification number: H04B17/102 ,  H03M1/0673 ,  H03M1/74

Abstract: Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.

Abstract translation: 用于将信号从模拟转换成数字的电路和方法。 随机数生成器为存储器提供随机数。 存储器被预配置为包括提供DAC梯度抑制的最大量的预定数模（DAC）配置的代码。 至少一个闪存参考生成DAC（FRGD）具有耦合到存储器单元的输入和为其各自的闪存比较器提供参考电压电平的输出。 闪存比较器将模拟输入信号与其各自的参考电压进行比较，并根据比较提供数字输出信号。

公开(公告)号：US09106202B2

公开(公告)日：2015-08-11

申请号：US14189652

申请日：2014-02-25

Applicant: Linear Technology Corporation

Inventor： Petrus M. Stroet

IPC: H03H7/48 ,  H03H7/21 ,  H04B15/02

CPC classification number: H03H7/21 ,  H04B15/02

Abstract: A poly-phase filter receives inphase input signals I and Ī and quadrature input signals Q and Q, and provides inphase output signals Iout and Iout and quadrature output signals Qout and Qout. The capacitance of each variable capacitor connected to the terminals providing inphase output signals Iout and Iout is and the capacitance of each variable capacitor connected to the terminals providing quadrature output signals Qout and Qout, are different in value, and preferably by twice a predetermined value. This is because adjustment to the capacitance values may be made to each set of variable capacitors by the predetermined value.

Abstract translation: 多相滤波器接收同相输入信号I和Ī和正交输入信号Q和Q，并提供同相输出信号Iout和Iout以及正交输出信号Qout和Qout。 连接到提供同相输出信号Iout和Iout的端子的每个可变电容器的电容是连接到提供正交输出信号Qout和Qout的端子的每个可变电容器的电容值，并且优选地是预定值的两倍。 这是因为可以通过预定值对每组可变电容器调整电容值。

公开(公告)号：US20150207423A1

公开(公告)日：2015-07-23

申请号：US14160831

申请日：2014-01-22

Applicant: Linear Technology Corporation

Inventor： Niranjan Ganesh Kumar

IPC: H02M3/335 ,  H02M1/08

CPC classification number: H02M3/33592 ,  H02M3/33553 ,  H02M2001/0009 ,  H02M2001/0032 ,  Y02B70/1475 ,  Y02B70/16

Abstract: A forward converter has a primary side containing a PWM controller for controlling switching of a power switch and has a secondary side coupled to the primary side via a transformer. The secondary side includes a forward transistor and a catch transistor. A secondary side switch controller controls switching of the forward transistor and the catch transistor without communication from the primary side. The secondary side switch controller detects the rising and falling of the voltages at the ends of the secondary winding to control the switching of the forward and catch transistors. A delay locked loop (DLL) is provided in the secondary side switch controller that turns on the catch transistor when the power switch is turned off and turns off the catch transistor at a predetermined time before the power switch is turned on. A separate circuit controls the catch transistor during a discontinuous mode.

Abstract translation: 正向转换器具有包含用于控制功率开关的开关的PWM控制器的初级侧，并且具有经由变压器耦合到初级侧的次级侧。 次级侧包括正向晶体管和捕获晶体管。 次级侧开关控制器控制正向晶体管和捕获晶体管的开关，而不与初级侧通信。 次级侧开关控制器检测次级绕组端部的电压的上升和下降以控制正向和捕获晶体管的切换。 在次级侧开关控制器中提供延迟锁定环（DLL），其在电源开关断开时接通捕获晶体管，并且在电源开关接通之前的预定时间关闭捕获晶体管。 单独的电路在不连续模式期间控制捕获晶体管。

公开(公告)号：US09078317B1

公开(公告)日：2015-07-07

申请号：US14332830

申请日：2014-07-16

Applicant: Linear Technology Corporation

Inventor： Keith D. Szolusha

IPC: H05B37/02 ,  H05B33/08

CPC classification number: H05B33/0815

Abstract: An LED driver uses a positive-to-floating boost converter topology to generate a negative voltage −Vee relative to ground. The converter receives an input voltage. Vin from a power supply. One end of an output inductor is coupled to ground, and the other end of the inductor is coupled between a highside switch and a low side switch. The bottom terminal of the lowside switch generates −Vee. The anode end of an LED string is coupled to Vin and the cathode end is coupled to −Vee. The converter detects the LED current and regulates the switching duty cycle so that the LED current is equal to a target current. This is more efficient than coupling the anode end of an LED string to ground and the cathode end to −Vee. A conventional buck controller IC may be used.

Abstract translation: LED驱动器使用正浮置升压转换器拓扑来产生相对于地的负电压。 转换器接收输入电压。 Vin从电源。 输出电感器的一端耦合到地，并且电感器的另一端耦合在高侧开关和低侧开关之间。 低端开关的底端产生-Vee。 LED串的阳极端耦合到Vin，阴极端耦合到-Vee。 转换器检测LED电流并调节开关占空比，使LED电流等于目标电流。 这比将LED串的阳极端耦合到地和阴极端更有效。 可以使用传统的降压控制器IC。

公开(公告)号：US09072147B2

公开(公告)日：2015-06-30

申请号：US14264518

申请日：2014-04-29

Applicant: Linear Technology Corporation

Inventor： Keith D. Szolusha ,  Joshua W. Caldwell ,  Bryan Legates

IPC: H05B33/08 ,  H05B41/28

CPC classification number: H05B33/0851 ,  H05B33/0809 ,  H05B33/0815 ,  H05B33/0818 ,  H05B41/28 ,  Y02B20/346 ,  Y02B20/347

Abstract: In a method for controlling a current regulator for dimming an LED load, a dimming signal has a duty cycle that controls the LED ON-time and LED OFF time at a fixed frequency. The regulator is controlled by the dimming signal to only supply current to the LED load during the LED ON-time. The regulator includes an inductor. The inductor current at the end of an ON-time is detected and its value is stored. During the OFF-time, the inductor is pre-charged to the current level matching the stored value, while the regulator's feedback loop is frozen during the OFF-time to not change its feedback control signal. Upon the next ON-time, the regulator begins supplying current to the LED load with the pre-charged inductor current, so there is no initial decrease in the delivered LED current. Therefore, the current pulse magnitudes are constant even with very low duty cycles.

Abstract translation: 在用于控制用于调光LED负载的电流调节器的方法中，调光信号具有以固定频率控制LED接通时间和LED关闭时间的占空比。 调光器由调光信号控制，以便在LED接通时间期间仅向LED负载提供电流。 调节器包括电感器。 检测接通时间结束时的电感电流，并存储其值。 在关断期间，电感器预充电到与存储值匹配的电流电平，而稳压器的反馈环路在关断时间冻结，不改变其反馈控制信号。 在下一个导通时间后，调节器开始向预充电电感电流的LED负载供电，因此LED电流的传送没有初始减少。 因此，即使在非常低的占空比下，当前脉冲幅度也是恒定的。