公开(公告)号：US11755521B2

公开(公告)日：2023-09-12

申请号：US17809688

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F13/4022 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US11755508B2

公开(公告)日：2023-09-12

申请号：US17507588

申请日：2021-10-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Craig E. Hampel ,  Scott C. Best ,  John Yan

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1673 ,  G06F13/1694

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

公开(公告)号：US20230282266A1

公开(公告)日：2023-09-07

申请号：US18181185

申请日：2023-03-09

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/022 ,  G11C29/028 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US11750426B2

公开(公告)日：2023-09-05

申请号：US17864100

申请日：2022-07-13

Applicant: Rambus Inc.

Inventor： Kamran Farzan ,  Dongyun Lee

IPC: H04L27/04 ,  H04L27/08

CPC classification number: H04L27/04 ,  H04L27/08

Abstract: A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.

公开(公告)号：US11750359B2

公开(公告)日：2023-09-05

申请号：US17676425

申请日：2022-02-21

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0332 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0037

Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

公开(公告)号：US20230266385A1

公开(公告)日：2023-08-24

申请号：US18157344

申请日：2023-01-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G01R31/28 ,  G01R31/317 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C29/50 ,  G01R31/26 ,  H03L7/00

CPC classification number: G01R31/2882 ,  G01R31/31726 ,  G11C29/022 ,  G11C29/12015 ,  G11C29/16 ,  G11C29/50012 ,  G01R31/2607 ,  H03L7/00 ,  G11C2029/0401

Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

公开(公告)号：US11735287B2

公开(公告)日：2023-08-22

申请号：US18074188

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/00 ,  G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US11734106B2

公开(公告)日：2023-08-22

申请号：US17852272

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/52 ,  G11C29/00 ,  H03M13/15 ,  G06F11/20

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  H03M13/1575 ,  G06F11/20 ,  G11C29/765 ,  G11C2029/4402

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

公开(公告)号：US11728835B2

公开(公告)日：2023-08-15

申请号：US17463897

申请日：2021-09-01

Applicant: RAMBUS INC.

Inventor： Kamran Farzan

IPC: H04B1/04 ,  H04B1/00

CPC classification number: H04B1/0483 ,  H04B1/0028

Abstract: An apparatus including a signal generation circuitry to provide a stream of digital signals carrying data. The apparatus includes a storage circuitry to provide a plurality of transmit levels corresponding to respective predetermined equalization levels; selection circuitry to select a transmit level from among the plurality of transmit levels based on the digital signals carrying data. Each of the plurality of transmit levels is a respective input signal to the selection circuitry. The apparatus includes a digital-to-analog converter (DAC) circuitry configured to receive the selected transmit level and convert the selected transmit level to an analog signal of the selected transmit level.

公开(公告)号：US11710520B2

公开(公告)日：2023-07-25

申请号：US17702475

申请日：2022-03-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  James E. Harris

IPC: G11C8/12 ,  G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C8/12

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.