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    Oscillator frequency adjustment
    91.
    发明授权
    Oscillator frequency adjustment 有权

    公开(公告)号：US11817870B2

    公开(公告)日：2023-11-14

    申请号：US17265980

    申请日：2019-08-19

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Volker Langer ,  Thomas Kattwinkel

    IPC: H03L7/181 ,  H03K3/353

    CPC classification number: H03L7/181 ,  H03K3/353

    Abstract: Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscillator. The frequency adjustment circuit comprises a counter configured to count a number of pulses generated by the free-running oscillator and logic configured to compare the number of pulses with an expected number of pulses (corresponding to a target frequency) to determine a difference value and to adjust the frequency of the free-running oscillator in dependence on the difference value. The frequency adjustment circuit is configured, in response to receiving a synchronisation pulse, to trigger an update of the number of pulses to be compared.

    SEMICONDUCTOR DEVICE
    93.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230352382A1

    公开(公告)日：2023-11-02

    申请号：US18170678

    申请日：2023-02-17

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Takashi KARASHIMA

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16

    CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L23/3128 ,  H01L23/16 ,  H01L2224/48227 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73265 ,  H01L24/73

    Abstract: A wiring substrate includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third conductive layer, a third insulating layer, and a fourth conductive layer. Given that an occupancy ratio of a first conductive pattern in the first conductive layer is a first occupancy ratio, an occupancy ratio of a second conductive pattern in the second conductive layer is a second occupancy ratio, an occupancy ratio of a third conductive pattern in the third conductive layer is a third occupancy ratio, and an occupancy ratio of a fourth conductive pattern in the fourth conductive layer is a fourth occupancy ratio, each of the first occupancy ratio and the third occupancy ratio is greater than each of the second occupancy ratio and the fourth occupancy ratio.

    Semiconductor device and method of manufacturing the same
    96.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US11798886B2

    公开(公告)日：2023-10-24

    申请号：US17938497

    申请日：2022-10-06

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hirokazu Sayama ,  Fumihiko Hayashi ,  Junjiro Sakai

    IPC: H01L23/535 ,  H01L21/74 ,  H01L21/762 ,  H01L21/764 ,  H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/764 ,  H01L21/76224

    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 μm.

    SEMICONDUCTOR DEVICE
    97.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230335635A1

    公开(公告)日：2023-10-19

    申请号：US17722788

    申请日：2022-04-18

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Yotaro GOTO

    IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/402

    Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

    SEMICONDUCTOR DEVICE
    98.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230335198A1

    公开(公告)日：2023-10-19

    申请号：US18299332

    申请日：2023-04-12

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hirofumi HEBISHIMA

    IPC: G11C16/16 ,  G11C16/34 ,  G11C16/32

    CPC classification number: G11C16/16 ,  G11C16/3413 ,  G11C16/32

    Abstract: A semiconductor device having an electrically writable or erasable non-volatile memory and a control circuit for executing mode control of a write operation and an erase operation of the non-volatile memory, in which the non-volatile memory has a rewrite suspension/recovery control circuit: responding to a suspension request signal from the control unit that requests a suspension of a rewrite operation; responding to an operation for suspending an application of a write voltage or an erase voltage and a recovery request signal from the control unit that requests a recovery from the suspension of the rewrite operation; controlling an operation for recovery from the suspension of the voltage application; and outputting a rewrite interruption/return control circuit that outputs to the control circuit a voltage application stop flag at a voltage application stop of the write voltage or erase voltage, and a rewrite information holding circuit that holds write position information for identifying a selection line to which a write voltage is applied at a response time of a suspension request signal.

    SYSTEMS INCLUDING BOUNDING BOX CHECKER FOR OBJECT DETECTION MARKING
    99.
    发明公开
    SYSTEMS INCLUDING BOUNDING BOX CHECKER FOR OBJECT DETECTION MARKING 审中-公开

    公开(公告)号：US20230326071A1

    公开(公告)日：2023-10-12

    申请号：US17718584

    申请日：2022-04-12

    Applicant: Renesas Electronics Corporation.

    Inventor： Shijia GUO ,  Stefan GELDREICH

    IPC: G06T7/73

    CPC classification number: G06T7/74 ,  G06T2207/10016 ,  G06T2207/30248

    Abstract: Systems and methods for evaluating a set of bounding boxes in a blended image are described. A system can include an integrated circuit configured to obtain expected bounding box data. The expected bounding box data can be based on coordinates data of an image. The integrated circuit can determine target coordinates based on the expected bounding box data. The integrated circuit can receive a blended image including a set of objects and a set of bounding boxes. The integrated circuit can extract pixel values located at the target coordinates in the blended image. The integrated circuit can identify an error relating to the set of bounding boxes based on the extracted pixel values and the expected bounding box data.

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