公开(公告)号：US11784173B2

公开(公告)日：2023-10-10

申请号：US17486301

申请日：2021-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko Akiba ,  Kenji Sakata ,  Nobuhiro Kinoshita ,  Yosuke Katsura

IPC: H01L23/02 ,  H01L25/16 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L25/165 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/05 ,  H01L24/16 ,  H01L24/27 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

公开(公告)号：US20160204082A1

公开(公告)日：2016-07-14

申请号：US15075128

申请日：2016-03-19

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Nobuhiro Kinoshita

IPC: H01L25/065

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2224/19 ,  H01L2224/05552

Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Abstract translation: 在通过将包括小直径的半导体芯片和具有大直径的半导体芯片的芯片层叠体安装在基板的顶表面上而形成的半导体器件中，防止了过度的应力被添加到两个半导体芯片的接头 。 通过在支撑基板上安装具有大直径的第一半导体芯片，然后在第一半导体芯片上安装具有小直径的第二半导体芯片，可以：抑制安装在第一半导体芯片上的第二半导体芯片的倾斜和不稳定性 半导体芯片; 并且因此抑制过多的应力被添加到第一半导体芯片和第二半导体芯片的接头。

公开(公告)号：US09349678B2

公开(公告)日：2016-05-24

申请号：US14750009

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro Ono ,  Nobuhiro Kinoshita ,  Tsuyoshi Kida ,  Jumpei Konno ,  Kenji Sakata ,  Kentaro Mori ,  Shinji Baba

IPC: H01L23/48 ,  H01L21/00 ,  B23K31/00 ,  H01L23/495 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49558 ,  H01L23/49811 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/06153 ,  H01L2224/06155 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/32245 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2224/45147

Abstract: The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger.

Abstract translation: 提高了半导体器件的可靠性。 在覆盖有保护绝缘膜的焊盘的探针区域上形成探针标记。 并且，柱状电极具有形成在开口区域上的第一部分和从开口区域的上部在探针区域上延伸的第二部分。 此时，开口区域的中心位置从与接合手指相对的柱状电极的中心位置偏移。

公开(公告)号：US20140193954A1

公开(公告)日：2014-07-10

申请号：US14204988

申请日：2014-03-11

Applicant: Renesas Electronics Corporation

Inventor： Naoto Taoka ,  Atsushi Nakamura ,  Naozumi Morino ,  Toshikazu Ishikawa ,  Nobuhiro Kinoshita

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06515 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/14515 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/92247

Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).

Abstract translation: 要提高半导体器件的可靠性。 具有形成在其主表面上的多个焊盘的微计算机芯片（半导体芯片）以与芯片主表面相对的状态安装在布线基板的上表面上。 耦合到形成在衬底上表面上的多个端子（接合引线）的焊盘包括多个第一焊盘，其中与流过其它焊盘的电流不同的独特电流流过多个第二焊盘，其中电流 焊盘共同流动或不流动。 第一焊盘或第二焊盘中的一个的另一个第一焊盘布置在第一焊盘的旁边。 第一焊盘分别经由多个凸起（第一导电构件）电耦合到多个接合引线，而第二焊盘通过多个凸块（第二导电构件）接合到端子。

公开(公告)号：US12218044B2

公开(公告)日：2025-02-04

申请号：US17722823

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuhiro Kinoshita ,  Shuuichi Kariyazaki ,  Keita Tsuchiya

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. The first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. The second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

公开(公告)号：US11158617B2

公开(公告)日：2021-10-26

申请号：US16444933

申请日：2019-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko Akiba ,  Kenji Sakata ,  Nobuhiro Kinoshita ,  Yosuke Katsura

IPC: H01L23/02 ,  H01L25/16 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

公开(公告)号：US09640414B2

公开(公告)日：2017-05-02

申请号：US15075128

申请日：2016-03-19

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Nobuhiro Kinoshita

IPC: H01L21/50 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/683 ,  H01L23/528

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2224/19 ,  H01L2224/05552

Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US09455240B2

公开(公告)日：2016-09-27

申请号：US14138164

申请日：2013-12-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L23/488 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/743 ,  H01L24/97 ,  H01L2224/10175 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Abstract translation: 提高了半导体器件的可靠性。 形成在布线基板中的芯片安装面上的多个端子中的每一个在平面图中具有窄宽度部分布置在相邻的宽幅部分之间的形状。 此外，形成在安装在布线基板上的半导体芯片上的多个突起电极中的每一个的前端面的中心布置在与平面图中的窄宽度部分重叠的位置，并且多个端子和 多个突出电极经由焊料构件彼此电连接。

公开(公告)号：US09355869B2

公开(公告)日：2016-05-31

申请号：US13969542

申请日：2013-08-17

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Nobuhiro Kinoshita

IPC: H01L21/50 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/683 ,  H01L23/528

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2224/19 ,  H01L2224/05552

Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Abstract translation: 在通过将包括小直径的半导体芯片和具有大直径的半导体芯片的芯片层叠体安装在基板的顶表面上而形成的半导体器件中，防止了过度的应力被添加到两个半导体芯片的接头 。 通过在支撑基板上安装具有大直径的第一半导体芯片，然后在第一半导体芯片上安装具有小直径的第二半导体芯片，可以：抑制安装在第一半导体芯片上的第二半导体芯片的倾斜和不稳定性 半导体芯片; 并且因此抑制过多的应力被添加到第一半导体芯片和第二半导体芯片的接头。

公开(公告)号：US09818678B2

公开(公告)日：2017-11-14

申请号：US14222649

申请日：2014-03-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.