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公开(公告)号:US11784173B2
公开(公告)日:2023-10-10
申请号:US17486301
申请日:2021-09-27
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Toshihiko Akiba , Kenji Sakata , Nobuhiro Kinoshita , Yosuke Katsura
IPC: H01L23/02 , H01L25/16 , H01L23/367 , H01L23/00 , H01L23/498 , H01L25/10
CPC classification number: H01L25/165 , H01L23/3675 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L24/32 , H01L24/05 , H01L24/16 , H01L24/27 , H01L24/33 , H01L24/73 , H01L24/83 , H01L25/105 , H01L2224/0401 , H01L2224/05083 , H01L2224/05084 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/32225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2924/19041 , H01L2924/19105
Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.
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公开(公告)号:US10128129B2
公开(公告)日:2018-11-13
申请号:US15621226
申请日:2017-06-13
Applicant: Renesas Electronics Corporation
Inventor: Toshihiko Akiba , Hiromi Shigihara , Kei Yajima
IPC: H01L21/48 , H01L23/00 , H01L23/31 , H01L23/538 , H01L23/498 , H01L23/525
Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.
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公开(公告)号:US09711377B2
公开(公告)日:2017-07-18
申请号:US14886088
申请日:2015-10-18
Applicant: Renesas Electronics Corporation
Inventor: Toshihiko Akiba , Hiromi Shigihara , Kei Yajima
IPC: H01L21/48 , H01L23/31 , H01L23/538 , H01L23/00 , H01L23/498 , H01L23/525
CPC classification number: H01L21/4889 , H01L21/4846 , H01L21/4853 , H01L23/3114 , H01L23/49816 , H01L23/525 , H01L23/5384 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/19 , H01L24/20 , H01L2224/03 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/11 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/73267 , H01L2224/92247 , H01L2224/94 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.
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公开(公告)号:US20160336244A1
公开(公告)日:2016-11-17
申请号:US15219254
申请日:2016-07-25
Applicant: Renesas Electronics Corporation
Inventor: Toshihiko Akiba , Bunji Yasumura , Masanao Sato , Hiromi Abe
CPC classification number: H01L22/32 , G01R31/26 , H01L22/14 , H01L22/20 , H01L22/30 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/02166 , H01L2224/02313 , H01L2224/02371 , H01L2224/02373 , H01L2224/02381 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/0603 , H01L2224/06133 , H01L2224/06135 , H01L2224/10 , H01L2224/1132 , H01L2224/11334 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/4911 , H01L2224/49429 , H01L2224/49431 , H01L2224/73204 , H01L2224/73265 , H01L2224/85951 , H01L2225/0651 , H01L2225/06517 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/05042 , H01L2924/10329 , H01L2924/12041 , H01L2924/1306 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2224/48744 , H01L2924/00012
Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
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公开(公告)号:US09293436B2
公开(公告)日:2016-03-22
申请号:US14711014
申请日:2015-05-13
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Toshihiko Akiba , Akihiro Tobita , Yuki Yagyu
CPC classification number: H01L24/05 , H01L21/4885 , H01L22/14 , H01L22/32 , H01L24/03 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/97 , H01L2224/02166 , H01L2224/0382 , H01L2224/03831 , H01L2224/04042 , H01L2224/05124 , H01L2224/05555 , H01L2224/05578 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05673 , H01L2224/05684 , H01L2224/16012 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/8501 , H01L2224/85375 , H01L2224/97 , H01L2924/01022 , H01L2924/01029 , H01L2924/01074 , H01L2924/013 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
Abstract: A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.
Abstract translation: 一种BGA的制造方法,包括以下步骤:提供具有电极焊盘的半导体芯片; 并除去形成在每个电极焊盘的表面上的自然氧化膜。 此外,在通过去除天然氧化膜而暴露的电极焊盘的表面上形成由导电部件构成的第一膜,电线与第一膜连接,并且电线的一部分与电极焊盘接触, 在导线和电极焊盘之间的界面处形成合金层。 第一膜的晶体结构由体心立方晶格或六方密堆积晶格组成。 可以降低半导体器件的成本,同时确保半导体器件的引线接合的接合可靠性。
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公开(公告)号:US11063009B2
公开(公告)日:2021-07-13
申请号:US15888846
申请日:2018-02-05
Applicant: Renesas Electronics Corporation
Inventor: Kenji Sakata , Toshihiko Akiba , Takuo Funaya , Hideaki Tsuchiya , Yuichi Yoshida
IPC: H01L23/00 , H01L23/498 , H01L23/31 , H01L23/29
Abstract: There is a need to improve reliability of the semiconductor device.
A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.-
公开(公告)号:US10163791B2
公开(公告)日:2018-12-25
申请号:US15721784
申请日:2017-09-30
Applicant: Renesas Electronics Corporation
Inventor: Toshihiko Akiba , Shuuichi Kariyazaki
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L23/528 , H01L23/15 , H01L23/00 , H01L23/498 , H01L25/065 , H01L25/18
Abstract: It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.
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公开(公告)号:US10134648B2
公开(公告)日:2018-11-20
申请号:US15876833
申请日:2018-01-22
Applicant: Renesas Electronics Corporation
Inventor: Toshihiko Akiba , Bunji Yasumura , Masanao Sato , Hiromi Abe
IPC: H01L21/66 , H01L23/00 , H01L25/065 , G01R31/26
Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
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公开(公告)号:US20180145001A1
公开(公告)日:2018-05-24
申请号:US15876833
申请日:2018-01-22
Applicant: Renesas Electronics Corporation
Inventor: Toshihiko Akiba , Bunji Yasumura , Masanao Sato , Hiromi Abe
CPC classification number: H01L22/32 , G01R31/26 , H01L22/14 , H01L22/20 , H01L22/30 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/02166 , H01L2224/02313 , H01L2224/02371 , H01L2224/02373 , H01L2224/02381 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/0603 , H01L2224/06133 , H01L2224/06135 , H01L2224/10 , H01L2224/1132 , H01L2224/11334 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/4911 , H01L2224/49429 , H01L2224/49431 , H01L2224/73204 , H01L2224/73265 , H01L2224/85951 , H01L2225/0651 , H01L2225/06517 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/05042 , H01L2924/10329 , H01L2924/12041 , H01L2924/1306 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2224/48744 , H01L2924/00012
Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
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公开(公告)号:US20160035636A1
公开(公告)日:2016-02-04
申请号:US14876787
申请日:2015-10-06
Applicant: Renesas Electronics Corporation
Inventor: Toshihiko Akiba , Bunji Yasumura , Masanao Sato , Hiromi Abe
CPC classification number: H01L22/32 , G01R31/26 , H01L22/14 , H01L22/20 , H01L22/30 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/02166 , H01L2224/02313 , H01L2224/02371 , H01L2224/02373 , H01L2224/02381 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/0603 , H01L2224/06133 , H01L2224/06135 , H01L2224/10 , H01L2224/1132 , H01L2224/11334 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/48744 , H01L2224/4911 , H01L2224/49429 , H01L2224/49431 , H01L2224/73204 , H01L2224/73265 , H01L2224/85951 , H01L2225/0651 , H01L2225/06517 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/05042 , H01L2924/10329 , H01L2924/12041 , H01L2924/1306 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H05K999/99 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2924/00012
Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
Abstract translation: 提供了一种在半导体芯片上具有焊盘的半导体器件,形成在半导体芯片上并且在探针区域的焊盘上的开口部分和耦合区域的第一钝化膜,形成在焊盘上的第二钝化膜和第一钝化膜 钝化膜并且在耦合区域的焊盘上具有开口部分,以及重新布线层,形成在耦合区域和第二钝化膜上并电耦合到焊盘。 相对于耦合区域放置在半导体芯片的周边侧的探针区域的焊盘具有探针标记,并且重新布线层从半导体芯片的耦合区域延伸到中心侧。 本发明提供能够实现半导体器件的尺寸减小,特别是间距变窄的技术。
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