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    Method of manufacturing semiconductor device
    2.
    发明授权
    Method of manufacturing semiconductor device 有权

    公开(公告)号：US10128129B2

    公开(公告)日：2018-11-13

    申请号：US15621226

    申请日：2017-06-13

    Applicant: Renesas Electronics Corporation

    Inventor： Toshihiko Akiba ,  Hiromi Shigihara ,  Kei Yajima

    IPC: H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/525

    Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11063009B2

    公开(公告)日：2021-07-13

    申请号：US15888846

    申请日：2018-02-05

    Applicant: Renesas Electronics Corporation

    Inventor： Kenji Sakata ,  Toshihiko Akiba ,  Takuo Funaya ,  Hideaki Tsuchiya ,  Yuichi Yoshida

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

    Abstract: There is a need to improve reliability of the semiconductor device.
    A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10163791B2

    公开(公告)日：2018-12-25

    申请号：US15721784

    申请日：2017-09-30

    Applicant: Renesas Electronics Corporation

    Inventor： Toshihiko Akiba ,  Shuuichi Kariyazaki

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L23/15 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

    Abstract: It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands.

    Manufacturing method of semiconductor device
    8.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US10134648B2

    公开(公告)日：2018-11-20

    申请号：US15876833

    申请日：2018-01-22

    Applicant: Renesas Electronics Corporation

    Inventor： Toshihiko Akiba ,  Bunji Yasumura ,  Masanao Sato ,  Hiromi Abe

    IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  G01R31/26

    Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

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