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公开(公告)号:US11063009B2
公开(公告)日:2021-07-13
申请号:US15888846
申请日:2018-02-05
Applicant: Renesas Electronics Corporation
Inventor: Kenji Sakata , Toshihiko Akiba , Takuo Funaya , Hideaki Tsuchiya , Yuichi Yoshida
IPC: H01L23/00 , H01L23/498 , H01L23/31 , H01L23/29
Abstract: There is a need to improve reliability of the semiconductor device.
A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.-
公开(公告)号:US09905529B2
公开(公告)日:2018-02-27
申请号:US15058282
申请日:2016-03-02
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Kenji Sakata , Tsuyoshi Kida , Yoshihiro Ono
IPC: H01L23/48 , H01L21/56 , H01L23/00 , H01L25/065
CPC classification number: H01L24/81 , H01L23/147 , H01L23/3675 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/83 , H01L24/92 , H01L25/0652 , H01L2224/1146 , H01L2224/11849 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16238 , H01L2224/2732 , H01L2224/27436 , H01L2224/2919 , H01L2224/73104 , H01L2224/73204 , H01L2224/75251 , H01L2224/75305 , H01L2224/7565 , H01L2224/75745 , H01L2224/81022 , H01L2224/81132 , H01L2224/81191 , H01L2224/81203 , H01L2224/8121 , H01L2224/81355 , H01L2224/81444 , H01L2224/81815 , H01L2224/8183 , H01L2224/81862 , H01L2224/81986 , H01L2224/83191 , H01L2224/83192 , H01L2224/83862 , H01L2224/9205 , H01L2224/92125 , H01L2224/97 , H01L2924/351 , H01L2224/81 , H01L2924/00014 , H01L2924/014
Abstract: A method for manufacturing a semiconductor device includes the steps of mounting a Si interposer over a printed wiring substrate, plasma-cleaning an upper surface of the Si interposer, disposing an NCF over the upper surface of the Si interposer, and mounting a semiconductor chip over the upper surface of the Si interposer through the NCF. Also, the method includes the step of electrically coupling each of plural electrodes of a second substrate and each of plural electrode pads of the semiconductor chip with each other through plural bump electrodes by reflow, and the surface of the Si interposer is plasma-cleaned before attaching the NCF to the Si interposer.
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公开(公告)号:US10141273B2
公开(公告)日:2018-11-27
申请号:US15304015
申请日:2014-04-14
Applicant: Renesas Electronics Corporation
Inventor: Shinji Watanabe , Tsuyoshi Kida , Yoshihiro Ono , Kentaro Mori , Kenji Sakata , Yusuke Yamada
IPC: H01L25/065 , H01L23/00 , H01L23/31
Abstract: In a semiconductor device according to an embodiment, a second semiconductor chip is mounted on a first rear surface of a first semiconductor chip. Also, the first rear surface of the first semiconductor chip includes a first region in which a plurality of first rear electrodes electrically connected to the second semiconductor chip via a protrusion electrode are formed and a second region which is located on a peripheral side relative to the first region and in which a first metal pattern is formed. In addition, a protrusion height of the first metal pattern with respect to the first rear surface is smaller than a protrusion height of each of the plurality of first rear electrodes with respect to the first rear surface.
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公开(公告)号:US09054093B2
公开(公告)日:2015-06-09
申请号:US14287023
申请日:2014-05-24
Applicant: Renesas Electronics Corporation
Inventor: Yoshihiro Ono , Tsuyoshi Kida , Kenji Sakata
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L24/06 , H01L21/563 , H01L23/3128 , H01L23/3192 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49861 , H01L23/49894 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/02163 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05611 , H01L2224/05666 , H01L2224/1134 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13027 , H01L2224/13084 , H01L2224/131 , H01L2224/13155 , H01L2224/14104 , H01L2224/14164 , H01L2224/14179 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/325 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81801 , H01L2224/83102 , H01L2224/83192 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/01074 , H01L2224/11 , H01L2224/81 , H01L2224/83 , H01L2924/014
Abstract: A semiconductor chip and a wiring board are coupled to each other through conductor posts. The centers of conductor posts situated above openings at the outermost periphery shift from the centers of the openings in a direction away from the center of the semiconductor chip. When a region where each of the conductor posts and an insulating layer are overlapped with each other is designated as an overlapped region, the width of the overlapped region more on the inner side than the opening is smaller than the width of the overlapped region more on the outer side than the opening. Thus, while stress applied to the conductor posts is relaxed, coupling reliability between the semiconductor chip and the wiring board is retained.
Abstract translation: 半导体芯片和布线板通过导体柱彼此耦合。 位于最外周的开口上方的导体柱的中心在远离半导体芯片的中心的方向上从开口的中心偏移。 当每个导体柱和绝缘层彼此重叠的区域被指定为重叠区域时,内侧上比开口更多的重叠区域的宽度小于重叠区域的宽度 外侧比开口。 因此,在施加到导体柱的应力松弛的同时,保持了半导体芯片和布线板之间的耦合可靠性。
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公开(公告)号:US10312199B2
公开(公告)日:2019-06-04
申请号:US15941300
申请日:2018-03-30
Applicant: Renesas Electronics Corporation
Inventor: Shinji Watanabe , Tsuyoshi Kida , Yoshihiro Ono , Kentaro Mori , Kenji Sakata , Yusuke Yamada
Abstract: A manufacturing method of a semiconductor device includes preparing a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface, arranging a first adhesive on the first surface of the wiring substrate, and after the arranging of the first adhesive, mounting a first semiconductor chip, which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, on the first surface of the wiring substrate via the first adhesive.
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公开(公告)号:US20180226362A1
公开(公告)日:2018-08-09
申请号:US15941300
申请日:2018-03-30
Applicant: Renesas Electronics Corporation
Inventor: Shinji Watanabe , Tsuyoshi Kida , Yoshihiro Ono , Kentaro Mori , Kenji Sakata , Yusuke Yamada
CPC classification number: H01L23/562 , H01L23/31 , H01L23/3128 , H01L24/02 , H01L24/16 , H01L24/42 , H01L24/97 , H01L2224/16145 , H01L2224/16225 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099
Abstract: A manufacturing method of a semiconductor device includes preparing a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface, arranging a first adhesive on the first surface of the wiring substrate, and after the arranging of the first adhesive, mounting a first semiconductor chip, which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, on the first surface of the wiring substrate via the first adhesive.
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公开(公告)号:US11158617B2
公开(公告)日:2021-10-26
申请号:US16444933
申请日:2019-06-18
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Toshihiko Akiba , Kenji Sakata , Nobuhiro Kinoshita , Yosuke Katsura
IPC: H01L23/02 , H01L25/16 , H01L23/367 , H01L23/00 , H01L23/498 , H01L25/10
Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.
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公开(公告)号:US11784173B2
公开(公告)日:2023-10-10
申请号:US17486301
申请日:2021-09-27
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Toshihiko Akiba , Kenji Sakata , Nobuhiro Kinoshita , Yosuke Katsura
IPC: H01L23/02 , H01L25/16 , H01L23/367 , H01L23/00 , H01L23/498 , H01L25/10
CPC classification number: H01L25/165 , H01L23/3675 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L24/32 , H01L24/05 , H01L24/16 , H01L24/27 , H01L24/33 , H01L24/73 , H01L24/83 , H01L25/105 , H01L2224/0401 , H01L2224/05083 , H01L2224/05084 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/32225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2924/19041 , H01L2924/19105
Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.
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9.
公开(公告)号:US09349678B2
公开(公告)日:2016-05-24
申请号:US14750009
申请日:2015-06-25
Applicant: Renesas Electronics Corporation
Inventor: Yoshihiro Ono , Nobuhiro Kinoshita , Tsuyoshi Kida , Jumpei Konno , Kenji Sakata , Kentaro Mori , Shinji Baba
IPC: H01L23/48 , H01L21/00 , B23K31/00 , H01L23/495 , H01L23/544 , H01L23/00
CPC classification number: H01L23/49568 , H01L22/32 , H01L23/3128 , H01L23/4951 , H01L23/4952 , H01L23/49558 , H01L23/49811 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/45 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L2223/5442 , H01L2223/54426 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0392 , H01L2224/0401 , H01L2224/05022 , H01L2224/05166 , H01L2224/05572 , H01L2224/05583 , H01L2224/05624 , H01L2224/05666 , H01L2224/06153 , H01L2224/06155 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13027 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/16105 , H01L2224/16225 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/8113 , H01L2224/81191 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06565 , H01L2924/00011 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2224/81 , H01L2224/83 , H01L2224/32245 , H01L2924/00012 , H01L2924/00 , H01L2924/00014 , H01L2924/014 , H01L2924/01074 , H01L2924/013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2224/45147
Abstract: The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger.
Abstract translation: 提高了半导体器件的可靠性。 在覆盖有保护绝缘膜的焊盘的探针区域上形成探针标记。 并且,柱状电极具有形成在开口区域上的第一部分和从开口区域的上部在探针区域上延伸的第二部分。 此时,开口区域的中心位置从与接合手指相对的柱状电极的中心位置偏移。
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公开(公告)号:US20140361430A1
公开(公告)日:2014-12-11
申请号:US14287023
申请日:2014-05-24
Applicant: Renesas Electronics Corporation
Inventor: Yoshihiro Ono , Tsuyoshi Kida , Kenji Sakata
IPC: H01L23/498
CPC classification number: H01L24/06 , H01L21/563 , H01L23/3128 , H01L23/3192 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49861 , H01L23/49894 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/02163 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05556 , H01L2224/05558 , H01L2224/05572 , H01L2224/05611 , H01L2224/05666 , H01L2224/1134 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13017 , H01L2224/13022 , H01L2224/13027 , H01L2224/13084 , H01L2224/131 , H01L2224/13155 , H01L2224/14104 , H01L2224/14164 , H01L2224/14179 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/325 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81801 , H01L2224/83102 , H01L2224/83192 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2924/01074 , H01L2224/11 , H01L2224/81 , H01L2224/83 , H01L2924/014
Abstract: A semiconductor chip and a wiring board are coupled to each other through conductor posts. The centers of conductor posts situated above openings at the outermost periphery shift from the centers of the openings in a direction away from the center of the semiconductor chip. When a region where each of the conductor posts and an insulating layer are overlapped with each other is designated as an overlapped region, the width of the overlapped region more on the inner side than the opening is smaller than the width of the overlapped region more on the outer side than the opening. Thus, while stress applied to the conductor posts is relaxed, coupling reliability between the semiconductor chip and the wiring board is retained.
Abstract translation: 半导体芯片和布线板通过导体柱彼此耦合。 位于最外周的开口上方的导体柱的中心在远离半导体芯片的中心的方向上从开口的中心偏移。 当每个导体柱和绝缘层彼此重叠的区域被指定为重叠区域时,内侧上比开口更多的重叠区域的宽度小于重叠区域的宽度 外侧比开口。 因此,在施加到导体柱的应力松弛的同时,保持了半导体芯片和布线板之间的耦合可靠性。
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