公开(公告)号：US10236350B2

公开(公告)日：2019-03-19

申请号：US15067540

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Sudharshanan Raghunathan ,  Andy Chi-Hung Wei ,  Jason Eugene Stephens ,  Vikrant Kumar Chauhan ,  David Michael Permana

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/768

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.

公开(公告)号：US10211100B2

公开(公告)日：2019-02-19

申请号：US15469701

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Andre Labonte ,  Nicholas LiCausi ,  Guillaume Bouche ,  Chanro Park

IPC: H01L21/764 ,  H01L21/768

Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.

公开(公告)号：US20180277430A1

公开(公告)日：2018-09-27

申请号：US15469701

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Andre Labonte ,  Nicholas LiCausi ,  Guillaume Bouche ,  Chanro Park

IPC: H01L21/768 ,  H01L21/764

CPC classification number: H01L21/76879 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/7685

Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.

公开(公告)号：US10069011B2

公开(公告)日：2018-09-04

申请号：US15728615

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a FinFET device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate (RMG) module. In particular, the method involves forming a sacrificial gate over the channel region of a fin, and an interlayer dielectric over adjacent source/drain regions of the fin. An etch mask is then used to protect source/drain contact regions and enable the removal of the interlayer dielectric from outside of the protected area, e.g., between adjacent fins.

公开(公告)号：US10043703B2

公开(公告)日：2018-08-07

申请号：US15379605

申请日：2016-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Nicholas Vincent Licausi

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/033 ,  H01L23/532 ,  H01L21/302 ,  H01L21/308

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/302 ,  H01L21/308 ,  H01L21/31144 ,  H01L23/528 ,  H01L23/5286

Abstract: A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines, the line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. An overall cell height of the cell is substantially equal to an integer multiple of a plurality of cell tracks, each cell track being a minimum pitch of the cell. The minimum pitch being defined by the minimum line width plus the minimum line spacer width. The minimum pitch is equal to or less than 36 nm. Not all of the line widths are substantially equal and every other line spacer width is substantially equal.

公开(公告)号：US20180113975A1

公开(公告)日：2018-04-26

申请号：US15791210

申请日：2017-10-23

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Guillaume Bouche ,  Julien Ryckaert

IPC: G06F17/50 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/84 ,  H01L27/02 ,  H01L27/11 ,  H01L27/12

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

公开(公告)号：US09852984B2

公开(公告)日：2017-12-26

申请号：US15207652

申请日：2016-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Wei ,  Sudharshanan Raghunathan

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

公开(公告)号：US09825031B1

公开(公告)日：2017-11-21

申请号：US15229292

申请日：2016-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy C. Wei ,  Jason E. Stephens ,  David M. Permana ,  Jagannathan Vasudevan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768

CPC classification number: H01L27/0886 ,  H01L21/76843 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795

Abstract: A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a liner layer. A first conductive feature is formed in the first contact opening and a second conductive feature is formed in the second contact opening. A portion of the liner layer adjacent a top surface of the first dielectric layer is removed to define a recess. A barrier layer is formed above the first dielectric layer and in the recess. The barrier layer has a first dielectric constant greater than a second dielectric constant of the first dielectric layer. A second dielectric layer is formed above the barrier layer. A third conductive feature is formed embedded in the second dielectric layer and contacting the second conductive feature.

公开(公告)号：US09812324B1

公开(公告)日：2017-11-07

申请号：US15405789

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Zhuang ,  Lars Liebmann ,  Stuart A. Sieg ,  Fee Li Lie ,  Mahender Kumar ,  Shreesh Narasimha ,  Ahmed Hassan ,  Guillaume Bouche ,  Xintuo Dai

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/30 ,  H01L21/027 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L27/0207 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.

公开(公告)号：US09589829B1

公开(公告)日：2017-03-07

申请号：US14982872

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy M. Cao ,  Daniel Jaeger ,  Guillaume Bouche

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of fins on a semiconductor substrate by defining a plurality of trenches in the substrate. A first insulating material layer comprising silicon, oxygen and carbon is formed in the trenches between the plurality of fins. The first insulating material layer has an upper surface that is at a level that is below an upper surface of the fins. A second insulating material layer is formed above the first insulating material layer. The second insulating material layer is planarized to expose a top surface of the plurality of fins. The second insulating material layer is removed to expose the first insulating material layer.

Abstract translation: 一种方法包括通过在衬底中限定多个沟槽，在半导体衬底上形成多个翅片。 在多个翅片之间的沟槽中形成包括硅，氧和碳的第一绝缘材料层。 第一绝缘材料层的上表面位于翅片上表面的下方。 第二绝缘材料层形成在第一绝缘材料层的上方。 第二绝缘材料层被平坦化以暴露多个翅片的顶表面。 去除第二绝缘材料层以露出第一绝缘材料层。